Redistribution Wiring Structure to Prevent Etch Undercut Peeling
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Solution Overview
Problem
The existing wet etching process for forming redistribution lines in semiconductor packages often results in undercuts and peeling issues due to etchant penetration, compromising the structural stability of fine line width redistribution lines.
Innovation Solution
A semiconductor package design with a lower redistribution wiring layer featuring sequentially stacked barrier, seed, and plating patterns, where the barrier layer pattern is formed using an anisotropic etching process to prevent undercuts, ensuring the sidewall of the barrier layer extends beyond the seed layer, thereby enhancing structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet etching process is used to form redistribution lines, then the redistribution lines can be formed with fine line width, but undercuts are generated in the seed layer and barrier layer causing peeling
Solution Approach 1:
The patent changes the etching process parameter from wet etching to dry etching. This parameter change eliminates the undercut phenomenon while maintaining fine line width precision, thereby resolving the contradiction between manufacturing precision and structural stability.
Solution Approach 2:
The patent replaces the chemical wet etching process with a physical dry etching process. This substitution prevents etchant penetration and undercut formation, maintaining both fine line width and structural integrity of the redistribution lines.
2Ease of manufacture
If barrier layer and seed layer are partially removed by wet etching, then plating wiring line can be formed, but etchant penetrates the interface causing redistribution line peeling
Solution Approach 1:
The patent replaces wet etching with dry etching to form the plating wiring line. This substitution prevents etchant penetration at the barrier layer interface while still enabling proper plating wiring formation, thus maintaining both ease of manufacture and interface bonding reliability.
Solution Approach 2:
The patent introduces dry etching as an intermediary process between barrier layer formation and plating. This intermediary process removes the harmful effect of wet etchant penetration while preserving the necessary interface structure for reliable bonding.
3Manufacturing precision
If isotropic etching is used to form seed layer pattern, then the seed layer can be patterned, but undercuts are generated in the barrier layer
Solution Approach 1:
The patent replaces isotropic wet etching with anisotropic dry etching for seed layer patterning. This substitution maintains precise pattern formation while producing vertical sidewalls without undercuts, resolving the contradiction between pattern formation quality and sidewall profile.
Solution Approach 2:
The patent changes the etching anisotropy parameter from isotropic to anisotropic. This parameter change enables precise pattern formation with vertical sidewalls, eliminating undercut generation while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach secures the structural stability of fine redistribution wirings by preventing undercuts and ensuring the redistribution lines remain connected to the underlying insulating layer, reducing defects and improving the reliability of the semiconductor package.
Implementation Method 1
a portion of the barrier layer exposed by the plating pattern is removed by an anisotropic etching process
Implementation Method 2
a plating pattern is formed in the opening
Data Source
AI summary
A semiconductor package includes a lower redistribution wiring layer having first redistribution wirings stacked in at least two layers, a semiconductor chip disposed on the lower redistribution wiring layer and electrically connected to the first redistribution wirings, a sealing member covering the semiconductor chip on the lower redistribution wiring layer, a plurality of through vias penetrating the sealing member and electrically connected to the first redistribution wirings, and an upper redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of through vias. Each of the first redistribution wirings includes a barrier layer pattern, a seed layer pattern and a plating pattern sequentially stacked. From a plan view, a sidewall of the barrier layer pattern extends laterally beyond a sidewall of the seed layer pattern.