Reduced-Aliasing SEC Code for Multi-Bit Error Correction
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Solution Overview
Problem
Existing error correction codes (ECC) face limitations in correcting multiple bit errors, leading to aliasing errors where a 2-bit error can become a 3-bit error, and increasing the number of parity bits to improve power increases storage and circuitry demands.
Innovation Solution
The implementation of reduced aliasing single-error correction (SEC) codes with specific constraints in encoder and decoder circuitry, such as the use of a minimum-aliasing H-matrix, to minimize aliasing errors without increasing the number of parity bits, allowing for efficient error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of parity bits is increased to improve error correction capability, then the power of error detection and correction is improved, but the size of storage memory and encoding/decoding circuitry increases
Solution Approach 1:
The patent changes the structural parameters of the H-matrix (specifically the distribution of odd and even columns) to optimize error correction performance. By carefully selecting which columns are odd and which are even, the system achieves reduced aliasing probability without adding more parity bits, thus improving reliability while maintaining the same circuitry size.
Solution Approach 2:
The patent creates a composite error correction code structure by combining SEC (single error correction) with reduced aliasing capabilities. This is achieved by constructing the H-matrix as a composite of data columns and parity columns with specific properties, where the first through (n-2)th columns are even and the (n-1)th column is odd, creating a hybrid code that achieves multiple benefits from a unified structure.
2Reliability
If conventional SEC codes are used, then single bit errors can be corrected, but aliasing errors occur where 2-bit errors can become 3-bit errors
Solution Approach 1:
The patent applies preliminary anti-action by designing the H-matrix structure in advance to prevent aliasing errors before they can occur. The specific configuration where the first through (n-2)th columns are even and the (n-1)th column is odd creates a protective structure that inherently prevents 2-bit errors from being misinterpreted as 3-bit errors, thus eliminating the harmful aliasing effect before it can corrupt the data.
Solution Approach 2:
The patent applies local quality by assigning different properties to different columns of the H-matrix. Specifically, the first through (n-2)th columns have even parity properties while the (n-1)th column has odd parity properties. This localized differentiation in column properties enables the code to distinguish between different error patterns and prevents aliasing while maintaining single error correction capability.
Data Source
AI summary
Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.