Reduced-Area Sub-Pixel Circuit for Dense VR/AR Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display devices, particularly those used for virtual and augmented reality, face challenges in integrating components with a minimum width within a narrow area to achieve high pixels per inch due to design limitations.
Innovation Solution
A sub-pixel configuration with a reduced number of transistors, including a light emitting element and multiple transistors such as PMOS transistors, capacitors, and additional control transistors, which are integrated into a narrow area to manage driving currents and voltages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If components are integrated in a narrow area to achieve high pixels per inch, then pixel density is improved, but component integration becomes limited due to minimum width design rules
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar 2D layout to 3D vertical stacking of transistor components. Multiple transistor layers are stacked vertically above each other, allowing components to be arranged in the third dimension (height) rather than only in the horizontal plane. This enables high pixel density while satisfying minimum width design rules, as components occupy vertical space instead of competing for horizontal area.
Solution Approach 2:
The patent implements nesting by placing multiple transistor components within a compact vertical structure where smaller components are positioned within or adjacent to larger ones in the vertical dimension. The nested arrangement allows TM1, TM2, TM3, and other components to be tightly integrated in a hierarchical fashion, maximizing space utilization while maintaining design rule compliance.
2Device complexity
If the number of transistors is reduced to simplify the sub-pixel configuration, then device complexity is reduced, but functionality may be compromised
Solution Approach 1:
The patent applies multi-functionality by designing transistors that perform multiple functions within the sub-pixel circuit. For example, certain transistors are configured to serve both as switching elements and as part of the compensation circuitry, or to function in different operational modes (e.g., initialization, data writing, emission control). This reduces the total transistor count while maintaining all necessary functions through clever circuit design where components perform multiple roles.
Solution Approach 2:
The patent merges functions by combining multiple transistor operations into fewer integrated components. Rather than having separate dedicated transistors for each function (initialization, compensation, emission), the design integrates these functions into a unified transistor structure where a single transistor or small group of transistors handles multiple operational tasks through different gate control signals and timing sequences.
Data Source
AI summary
A sub-pixel includes a light emitting element, a first transistor that applies a driving current to the light emitting element, a second transistor that writes a data voltage in response to a write gate signal, a first capacitor electrically connected to a control electrode of the first transistor, a second capacitor including a first electrode electrically connected to the second transistor and a second electrode electrically connected to the control electrode of the first transistor, a third transistor that diode-connects the first transistor in response to a compensation gate signal, a fourth transistor that applies a first initialization voltage to a first electrode of the third transistor in response to an initialization gate signal, and a fifth transistor that transfers the driving current to the light emitting element in response to an emission signal.