Reduced Capacitor DAC Topology for SAR ADC Offset Correction
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Solution Overview
Problem
Existing SAR ADCs face challenges in offset correction, as digital correction limits signal range, while analog and hybrid correction methods increase circuit complexity, necessitating a more efficient approach that does not require a dedicated compensation DAC.
Innovation Solution
A hybrid analog/digital offset correction method using a reduced capacitor array DAC, where offset correction capacitors are coupled to reference voltages, allowing for offset voltage compensation without additional analog circuitry, enabling offset correction without limiting the ADC's signal range or increasing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If digital offset correction is used in post-processing, then the correction method is simple, but the ADC's signal range is limited
Solution Approach 1:
The capacitor array is segmented into two functional groups: a first group of capacitors dedicated to offset correction and a second group for normal signal conversion. This segmentation allows the offset correction function to be performed without affecting the full signal range capability of the remaining capacitors, thereby resolving the contradiction between correction simplicity and signal range limitation.
2Adaptability or versatility
If analog offset correction using offset compensated comparator is used, then the ADC's signal range is maintained, but the circuit complexity is substantially increased
Solution Approach 1:
The offset correction function is merged with the existing capacitor array DAC structure. The first group of capacitors in the array performs dual functionality: offset correction during calibration and signal conversion during normal operation. This merging eliminates the need for separate offset compensated comparators or dedicated correction DACs, maintaining signal range while avoiding substantial circuit complexity increases.
3Adaptability or versatility
If hybrid analog/digital offset correction using dedicated correction DAC is used, then the ADC's signal range is maintained, but the circuit complexity is substantially increased
Solution Approach 1:
The capacitor array DAC is designed with universal functionality to perform both offset correction and signal conversion. By configuring the first group of capacitors to provide offset correction voltage during calibration and normal operation, the system eliminates the need for a dedicated correction DAC, thereby maintaining signal range without substantial circuit complexity increase.
4Device complexity
If reduced capacitor array DAC with offset correction capacitors is used, then offset correction is achieved without dedicated compensation DAC, but the capacitor array structure is modified
Solution Approach 1:
The capacitor array structure is made dynamically configurable through switch control. The switches enable the first group of capacitors to be connected to reference voltages for offset correction or to the input signal for normal conversion, depending on the operational phase. This dynamic reconfiguration allows the modified capacitor array structure to serve multiple functions without permanent structural changes that would increase complexity.
Data Source
AI summary
Offset correction in a differential successive approximation register (SAR) analog-to-digital converter (ADC) is accomplished with a capacitor-reduced digital-to-analog converter (DAC) topology to enable offset correction without the need for a dedicated compensation DAC. This eliminates addition analog circuitry and die area. To perform the offset correction, the differential SAR ADC couples together inputs thereof to create an offset voltage, converts the offset voltage into a digital representation thereof, stores the digital representation of the offset voltage in an offset register, and corrects for the offset voltage by generating an offset compensation voltage with the capacitor-reduced array DAC controlled by the digital representation stored in the offset register. The digital representation controls scaling of reference voltages to the reduced capacitor array DAC associated with a least-significant-bit (LSB) of the differential SAR ADC.