Reduced Control Binary Sequence for Constraint Root Cause Localization
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Solution Overview
Problem
The existing methods for functional verification of circuit designs, particularly for complex System-on-Chip (SoC) circuits, are time-consuming and inefficient, especially when identifying the root cause of error messages triggered by constraints during simulation.
Innovation Solution
A method that involves obtaining a control binary sequence from simulating a design under test (DUT) using a constraint random stimulus generator and a coverage biaser, then constructing a reduced control binary sequence with a subset of enabled bits to selectively restore solving steps of the constraint random stimulus generator, thereby identifying the constraints that trigger a designated message.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constraint random stimulus generator with coverage biaser is used to thoroughly test complex SoC circuits, then verification coverage and reliability are improved, but the time required to identify root cause of error messages increases significantly
Solution Approach 1:
The patent segments the constraint solving process by introducing a control binary sequence that divides constraints into enabled and disabled groups. This allows the verification process to focus on specific constraint segments that trigger error messages, rather than analyzing all constraints simultaneously. The segmentation enables targeted debugging by isolating problematic constraint regions.
Solution Approach 2:
The patent applies partial action by using the control binary sequence to selectively enable only certain constraint solving steps during re-simulation. Instead of re-running the complete simulation with all constraints enabled, the system performs partial re-simulation with only the necessary constraint segments activated, reducing the time required to identify root causes while maintaining verification effectiveness.
2Measurement precision
If multiple simulation runs are performed to localize constraints triggering error messages, then measurement precision is improved, but productivity decreases due to repeated full simulations
Solution Approach 1:
The patent performs preliminary action by generating and storing the control binary sequence during the initial simulation process. This control sequence captures the state of constraint solving steps and is preserved for use in subsequent re-simulation attempts. By having this preliminary control data ready, the system avoids re-collecting simulation state information and can directly proceed to targeted re-simulation, improving productivity while maintaining localization precision.
Solution Approach 2:
The patent creates a copy of the constraint solving state through the control binary sequence, which records which constraint solving steps were enabled during the original simulation. This binary copy allows the system to reproduce specific constraint solving scenarios without re-executing the entire simulation process, enabling precise constraint localization with reduced computational overhead.
3Reliability
If the complete control binary sequence is used for re-simulation, then accuracy of error reproduction is maintained, but computing resources are wasted on redundant simulation steps
Solution Approach 1:
The patent extracts only the necessary portion of the control binary sequence by identifying and isolating the enabled bits that correspond to constraint solving steps relevant to the error message. Instead of using the complete control binary sequence for re-simulation, the system extracts and applies only the minimal subset needed to reproduce the error condition, thereby reducing computing resource consumption while maintaining error reproduction accuracy.
Data Source
AI summary
In an example, a control binary sequence (CBS) determined during simulating a design under test (DUT) is obtained. Simulating included using a constraint random stimulus generator (CRSG) biased by a coverage biaser. The CBS includes first enabled bits that correspond to respective constraint problems solved by the CRSG and biased by the coverage biaser and from which a designated message was triggered during the simulating. A reduced CBS that has second enabled bits that are a subset of the first enabled bits is constructed. A simulation result generated by re-simulating the DUT is obtained. Re-simulating includes selectively, for each constraint problem, restoring solving steps of the CRSG that were performed during the simulating when a corresponding bit of the reduced CBS is an enabled bit. The reduced CBS is assigned as a triggering CBS that triggered the designated message when the simulation result includes the designated message.