Reduced Current Memory Device With Selectable Parallel Impedance Paths
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Solution Overview
Problem
Non-volatile memory devices, particularly RRAM, face challenges due to high write current requirements resulting from long bit lines with high capacitance, leading to power-hungry devices that reduce battery life in electronic products.
Innovation Solution
The implementation of a memory device with selectable parallel impedance paths, comprising switching elements with different doping levels and impedances, allows for reduced current consumption by dampening capacitive surge currents during certain operations and enabling lower impedance for high current needs, thereby conserving power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If long bit lines are used in RRAM devices, then memory capacity and addressing range are improved, but capacitive surge current increases导致write current requirements increase
Solution Approach 1:
The bit line is segmented into multiple shorter segments by inserting switching elements at intermediate points. This segmentation reduces the capacitive load on any single bit line segment, thereby reducing the capacitive surge current during write operations while maintaining the ability to address a large number of memory cells through the network of segmented lines.
Solution Approach 2:
Switching elements are introduced as intermediary components between the control logic and the memory cells. These switching elements act as mediators that can selectively connect or disconnect bit line segments, enabling precise control over which memory cells are accessed and reducing the total capacitive load that must be charged during write operations.
2Reliability
If high write current is used to break the wider filament during RESET operation, then memory cell switching reliability is improved, but power consumption increases reducing battery life
Solution Approach 1:
The impedance of bit line segments is made dynamic through the use of switching elements that can change their resistance states. During write operations, the switching elements dynamically adjust the impedance to optimize current distribution, ensuring sufficient current reaches the memory cell for reliable switching while minimizing total power consumption through adaptive impedance control.
Solution Approach 2:
The patent utilizes parameter changes in the switching elements' resistance states to control current flow. By transitioning switching elements between high-resistance and low-resistance states, the system can precisely control the amount of current directed to specific memory cells, enabling reliable cell switching when needed while reducing overall power consumption during idle or read operations.
3Use of energy by moving object
If capacitance of bit line is reduced to lower surge current, then write current requirements are reduced, but memory capacity or addressing range is limited
Solution Approach 1:
The memory array is divided into smaller blocks with shorter bit line segments. Each segment has reduced capacitance, lowering the surge current requirement. The segmentation is organized such that multiple segments can be independently controlled and accessed, allowing the system to maintain large total memory capacity while each individual segment operates with low capacitive load.
Solution Approach 2:
The patent employs a three-dimensional memory architecture where memory cells are arranged in multiple layers. This vertical dimensionality allows the system to increase memory capacity by stacking cells rather than expanding bit line length horizontally. Shorter bit line segments in each layer, combined with vertical stacking, achieve both low capacitive load and high memory capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the current required for memory operations, enhancing battery life and power efficiency in electronic products by managing impedance dynamically based on the specific operation type.
Implementation Method 1
dampening capacitive surge currents from long bit lines
Implementation Method 2
selectable first and second impedances between the bit line and the local bit lines
Implementation Method 3
enabling lower impedance for high current needs
Data Source
AI summary
A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.