Reduced-Size Die Bumping Stack for Lower Routing Congestion
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Solution Overview
Problem
Conventional semiconductor die bumping configurations face challenges in reducing die size due to congestion of metal layers, which can lead to increased complexity and cost in manufacturing, particularly with reduced lateral dimensions of conductive pads and metal layers.
Innovation Solution
The proposed bumping assembly features a metal layer with a lateral dimension less than the conductive pad, allowing for a reduction in die size by optimizing the lateral dimensions of the metal layer, conductive pad, and under bump metallization layer, while maintaining reliable electrical connections through a neck portion and similar footprint shapes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the lateral dimension of the metal layer is reduced to minimize die size, then the die size is reduced, but the electrical connection reliability between the metal layer and bump may deteriorate
Solution Approach 1:
The patent transitions from a two-dimensional reduction approach to a three-dimensional stacked configuration. By arranging the metal layer, conductive pad, and under bump metallization layer in vertical stacks with optimized lateral dimensions, the invention achieves die size reduction while maintaining reliable electrical connections through the bump structure.
Solution Approach 2:
The patent implements a nested configuration where the metal layer is positioned within the lateral boundaries of the conductive pad, which in turn is positioned within the lateral boundaries of the under bump metallization layer. This nested arrangement optimizes space utilization and ensures reliable electrical connection paths.
2Area of stationary object
If the lateral dimension of the metal layer is made smaller than the conductive pad, then metal layer congestion is reduced and die size is minimized, but manufacturing complexity may increase
Solution Approach 1:
The patent segments the bumping assembly into distinct functional layers (metal layer, conductive pad, under bump metallization layer) with different lateral dimensions. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall manufacturing feasibility through standardized processes.
Solution Approach 2:
The patent applies local quality by assigning different lateral dimensions to different layers based on their specific functional requirements. The metal layer has a smaller lateral dimension optimized for signal routing and congestion reduction, while the conductive pad and under bump metallization layer have larger dimensions optimized for electrical connection reliability.
3Area of stationary object
If the lateral dimension of the metal layer is reduced, then routing efficiency improves and die size decreases, but the congestion of metal layers may worsen if not properly managed
Solution Approach 1:
The patent resolves metal layer congestion by utilizing the vertical dimension to create stacked configurations. This allows multiple signal paths to be routed through different vertical levels, effectively increasing routing capacity without increasing the lateral footprint, thereby reducing overall die size while maintaining routing efficiency.
Data Source
AI summary
A reduced-size semiconductor die can be provided by a bumping assembly that includes one or more substrate layers, a metal layer formed over the one or more substrate layers, with the metal layer being configured for routing of a signal and having a lateral dimension, and a conductive pad formed over the metal layer and having a lateral dimension. The bumping assembly can further include an under bump metallization layer formed over the conductive pad and having a lateral dimension, such that the metal layer is electrically connected to a bump through the conductive pad and the under bump metallization layer when the bump is implemented over the under bump metallization layer, with the lateral dimension of the metal layer being less than the lateral dimension of the conductive pad.