Reduced Gate Charge FET With Segmented Dielectric Liner
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional trench MOSFETs face increased gate charge due to reduced cell pitch and increased power density, leading to higher switching losses and reduced switching speeds.
Innovation Solution
The method involves forming a reduced gate charge field-effect transistor by increasing the upper thickness of the dielectric liner in the gate trench, creating a thicker upper segment of the dielectric liner, and partially filling the gate trench with a conductive material to extend the gate electrode, thereby reducing gate charge and minimizing drain-induced barrier lowering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the cell pitch is reduced and power density is increased to reduce device size, then the device size is reduced, but the gate charge increases
Solution Approach 1:
The dielectric liner is segmented into two distinct segments: a first segment adjacent to the source region and a second segment adjacent to the drain region. This segmentation allows each segment to be independently optimized for thickness, with the first segment being thinner than the second segment, thereby reducing overall gate charge while maintaining device size reduction benefits
Solution Approach 2:
Different regions of the dielectric liner are given different thicknesses to optimize local electrical characteristics. The thinner first segment near the source reduces gate charge contribution from that region, while the thicker second segment near the drain maintains necessary electrical isolation and control, resolving the contradiction between device size reduction and gate charge increase
2Speed
If the gate charge is reduced to improve switching speed, then the switching speed is improved, but the device structure becomes more complex
Solution Approach 1:
The dielectric liner is divided into two segments with different thicknesses, where the first segment has a smaller thickness than the second segment. This segmentation reduces the total gate charge by removing excess dielectric material in the source region while maintaining necessary insulation in the drain region, thereby improving switching speed without requiring complex external circuit modifications
Solution Approach 2:
The thickness parameter of the dielectric liner is varied spatially along the gate trench, with the first segment having a reduced thickness compared to the second segment. This parameter change directly reduces gate charge and improves switching speed while the segmentation approach keeps the structural modification relatively simple and manufacturable
Data Source
AI summary
In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.