Reduced Height Gate Electrode for Low Parasitic Capacitance
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Solution Overview
Problem
Semiconductor structures with high parasitic gate capacitance reduce transistor performance by increasing signal delay, and existing methods to reduce this capacitance either compromise stress applied to the channel or use high dielectric constant materials, which are detrimental to MOSFET performance.
Innovation Solution
A semiconductor structure with a reduced height gate electrode and a low-k dielectric gate filler or cavity surrounded by the gate spacer, where the nitride liner contacts only the outer sidewalls of the gate spacer, reducing parasitic capacitance while maintaining channel stress similar to conventional FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the height of the gate electrode is reduced to reduce parasitic capacitance, then parasitic capacitance is reduced, but the stress applied to the channel is compromised
Solution Approach 1:
A stress liner is introduced as an intermediary layer between the gate electrode and the channel. This stress liner maintains the necessary mechanical stress on the channel even when the gate electrode height is reduced, thereby decoupling the relationship between gate height and channel stress.
Solution Approach 2:
The patent changes the material composition and physical properties of the gate electrode structure by introducing a stress liner with specific mechanical properties. This allows the gate electrode height to be reduced for lower parasitic capacitance while the stress liner compensates for the stress reduction that would otherwise occur.
2Ease of manufacture
If conventional gate electrode structures are used, then manufacturing is simpler, but parasitic capacitance and signal delay are higher
Solution Approach 1:
The gate electrode structure is segmented into distinct functional layers: the conductive gate electrode, the stress liner, and the low-k dielectric material. This segmentation allows each layer to be optimized for its specific function while maintaining a manufacturable multi-layer structure that can be integrated into existing fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance between the gate electrode and contact vias, minimizing signal delay while preserving the stress applied to the channel, thus enhancing MOSFET performance.
Implementation Method 1
Parasitic gate capacitance of a field effect transistor (FET) reduces the performance of the transistor by reducing the switching speed
Implementation Method 2
a low-k dielectric gate filler having a dielectric constant of about 3.0 or less
Data Source
AI summary
A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.