Reduced Layout Timing Analysis for Critical Path Verification
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Solution Overview
Problem
Current circuit design processes are time-intensive and inefficient, particularly in detecting and analyzing critical paths within circuit designs, as they require generating a full schematic model for every modification, which is cumbersome and time-consuming.
Innovation Solution
A system that detects a predetermined critical path in a circuit design, identifies inputs and outputs for associated macros, builds a reduced layout design, and generates a timing report, allowing for the manufacture of a circuit based on the report's conditions without needing a full schematic model, thereby enabling faster analysis and modification of critical paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full schematic model is generated for every modification to analyze critical paths, then timing analysis accuracy is improved, but analysis time and process complexity increase significantly
Solution Approach 1:
The patent segments the full circuit design into a reduced layout design that includes only the critical path components (macros, interconnects, and buffers) relevant to timing analysis. This segmentation allows timing analysis to be performed on a smaller, focused subset of the circuit rather than requiring a complete schematic model, thereby reducing analysis time while maintaining accuracy for the critical path.
Solution Approach 2:
The patent extracts the essential timing-critical elements (macros, interconnects, and buffers) from the complete circuit design to create a reduced layout design. By taking out only the necessary components for critical path analysis rather than using the full schematic, the method achieves accurate timing measurement without the time penalty of processing the entire circuit design.
2Reliability
If a full schematic model is generated for every modification, then complete circuit verification is improved, but device complexity and ease of operation deteriorate
Solution Approach 1:
The patent divides the circuit verification process into segments: a reduced layout design for critical path timing analysis and the full design for other verification aspects. This segmentation reduces process complexity for timing-critical modifications while maintaining reliability through targeted analysis of the critical path components.
Solution Approach 2:
The patent applies partial action by performing timing analysis on only the critical path portion of the circuit rather than the complete design. This partial verification approach is sufficient for timing-critical modifications, reducing process complexity while maintaining adequate reliability for the specific analysis goal.
3Productivity
If a reduced layout design is used instead of a full schematic model, then analysis speed is improved, but measurement precision may deteriorate
Solution Approach 1:
The patent applies local quality by creating a reduced layout design that concentrates detailed timing information specifically on the critical path components (macros, interconnects, and buffers) while using abstraction elsewhere. This localized detail ensures measurement precision is maintained for the timing-critical portions of the circuit while achieving overall analysis speed improvement.
Data Source
AI summary
Generating reports for critical path evaluation and tuning. A predetermined critical path in a circuit design is detected. The predetermined critical path includes a plurality of interconnects between at least two macros. At least one output or at least one input is detected for each of the at least two macros associated with the predetermined critical path. Additionally, a routing description and a buffer location corresponding to the predetermined critical path are detected and a reduced layout design is built. The reduced layout design includes the predetermined critical path and the at least two macros. Furthermore, a timing report is generated based on the reduced layout design, and a circuit based on the circuit design is manufactured in response to detecting the timing report based on the reduced layout design satisfies a predetermined condition.