Reduced Mask Count for 3D Stacked IC Contact Levels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3-D stacked memory devices require a separate mask for each contact level, leading to increased costs and complexity due to the need for multiple lithographic steps, which limits the efficiency of interconnect formation.
Innovation Solution
The use of a set of N masks allows for the creation of interconnect contact regions aligned with landing areas at up to 2N contact levels, reducing the number of masks and lithographic steps required by etching 2x−1 contact levels for each mask sequence number x, enabling efficient access and electrical connection to multiple levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate mask is used for each contact level, then access to each contact level can be achieved, but the number of masks and lithographic steps increases significantly
Solution Approach 1:
The patent combines multiple contact level accesses into a single mask by creating a mask pattern that defines contact openings for multiple levels simultaneously. The mask includes a first contact opening pattern for a first contact level and a second contact opening pattern for a second contact level, allowing both levels to be accessed through one lithographic step rather than requiring separate masks for each level.
Solution Approach 2:
The single mask serves multiple functions by providing access patterns for multiple contact levels. The mask pattern is designed to create openings that align with landing areas at different contact levels, making the mask universal for accessing multiple levels rather than requiring level-specific masks.
2Manufacturing precision
If multiple lithographic steps are used for each contact level, then precise alignment can be achieved, but manufacturing cost and process time increase
Solution Approach 1:
The patent merges multiple lithographic steps into a single step by designing a mask that contains all necessary contact opening patterns for multiple contact levels. This single lithographic step creates aligned contact openings simultaneously, maintaining precision while eliminating the need for multiple sequential steps.
Solution Approach 2:
The mask is designed in advance with pre-defined contact opening patterns that account for the vertical stacking of contact levels. The preliminary design of the mask pattern ensures that when a single lithographic step is performed, the resulting openings are correctly positioned for multiple levels without requiring subsequent alignment steps.
3Adaptability or versatility
If conventional interconnect structures are used for stacked contact levels, then each level can be accessed independently, but the area required for interconnects increases
Solution Approach 1:
The patent transitions from a horizontal layout approach to a vertical stacking approach by forming contact levels at different heights above the substrate. The single mask creates contact openings that access landing areas at multiple vertical levels, utilizing the vertical dimension to reduce the horizontal area required for interconnect structures.
Solution Approach 2:
The contact levels are nested vertically, with each subsequent contact level positioned above the previous one. The single mask pattern creates a nested structure where contact openings for different levels are vertically aligned, allowing compact interconnect design that accesses multiple levels within a small footprint.
Data Source
AI summary
A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x−1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.


