Reduced Netlist Floorplan Generation for Hierarchical Circuit Design
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Solution Overview
Problem
The complexity of digital circuit designs requires extensive and time-consuming iterations in generating a floorplan, especially for larger circuit designs, as the existing methods are computationally intensive and inefficient when using full netlists.
Innovation Solution
A system that generates a reduced netlist by focusing on interface logic elements, allowing for faster and more efficient floorplan generation while ensuring design constraints are met, using the reduced netlist to create a floorplan that satisfies timing, power, routing, area, and placement constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full netlist is used for floorplan generation, then the floorplan can be accurately analyzed to satisfy design constraints, but the computation time becomes excessively long for large circuit designs
Solution Approach 1:
The patent segments the full netlist into hierarchical blocks, where each block represents a functional unit with its own internal netlist. This segmentation allows the floorplanning process to work with coarse-grained block representations rather than the complete detailed netlist, significantly reducing computation time while preserving the ability to analyze critical timing paths within each block separately.
Solution Approach 2:
The patent extracts only the necessary interface logic and timing-critical paths from the full netlist to create a reduced netlist for floorplan generation. By taking out and retaining only the essential elements needed for floorplan analysis (such as interface pins, register locations, and critical timing paths), the system achieves accurate floorplan evaluation without processing the entire detailed netlist.
2Manufacturing precision
If detailed placement and routing are performed before floorplanning, then precise circuit implementation is achieved, but the iterative floorplanning process becomes extremely time-consuming
Solution Approach 1:
The patent performs preliminary floorplanning at the block level before detailed placement and routing. By establishing the overall arrangement of functional blocks and their interconnections in advance, the system creates a guiding framework that directs subsequent detailed placement. This preliminary action eliminates the need for repeated full detailed placement iterations, as the block-level floorplan provides stable guidance for detailed implementation.
3Reliability
If the floorplan generation process is made interactive with multiple iterations, then the floorplan characteristics can be refined to meet timing and routability constraints, but the total time required exceeds a work day for large designs
Solution Approach 1:
The patent applies local quality by performing detailed timing analysis and optimization only on critical paths and interface logic within each block, rather than uniformly processing the entire design. This allows the system to focus computational resources on the most timing-critical areas, achieving constraint satisfaction with fewer iterations and less total time.
Data Source
AI summary
One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist description for the hierarchical circuit design, and generate a reduced netlist which includes the interface logic elements of the netlist. The system can then generate the floorplan by using the reduced netlist as input. Note that the amount of computational resources and time required to generate a floorplan is substantially reduced because the system generates the floorplan using the reduced netlist instead of using the non-reduced netlist.