Reduced Symbol Occurrence Encoding for Hardware Data Compression
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Solution Overview
Problem
Existing data compression techniques, such as those using Asymmetric Numeral Systems (ANS), are not optimized for hardware-friendly implementations like Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs), as they rely on general-purpose CPUs for compression and decompression operations.
Innovation Solution
A lossless compression method using entropy encoding that involves determining the occurrences of distinct symbols in a data block, generating reduced occurrences, and encoding the data using these reduced values as a probability distribution, which can be implemented efficiently in hardware-friendly formats by utilizing a compressor with an input interface, calculator, and encoder engine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If existing ANS implementations are used, then compression ratio is improved, but hardware implementation complexity increases and processing speed decreases
Solution Approach 1:
The patent modifies the probability distribution parameters by using reduced occurrence counts instead of actual occurrence counts. This parameter change simplifies the arithmetic operations in hardware while maintaining effective compression. The encoder uses a simplified probability model that requires fewer computational steps, directly improving processing speed without significantly compromising compression ratio.
Solution Approach 2:
The patent employs simplified data structures and temporary variables that are discarded after use, rather than maintaining complex state information. The occurrence count table uses minimal memory resources and is regenerated for each data block, enabling fast processing with reduced hardware resource requirements.
2Loss of substance
If existing ANS implementations are used, then compression ratio is improved, but device complexity increases
Solution Approach 1:
The patent divides the compression process into distinct modular stages: occurrence counting, probability distribution generation, and encoding. Each stage is implemented as a separate hardware module with clearly defined inputs and outputs. This segmentation allows for independent optimization and simplifies the overall hardware architecture by eliminating the need for complex integrated processing units.
Solution Approach 2:
The patent replaces complex arithmetic operations with simpler logic operations suitable for hardware implementation. Instead of using floating-point arithmetic or complex integer operations, the system uses bit manipulation and integer arithmetic that can be efficiently implemented in FPGA or ASIC logic circuits, significantly reducing device complexity.
3Adaptability or versatility
If general-purpose CPU is used, then adaptability is improved, but processing speed and hardware cost worsen
Solution Approach 1:
The patent designs a universal encoding algorithm that can be implemented across different hardware platforms including FPGA, ASIC, and embedded systems. The core logic operations and data structures are platform-agnostic, allowing the same design to be deployed on various hardware architectures with optimized processing speeds and reduced costs compared to general-purpose CPU implementations.
Data Source
AI summary
Systems, apparatus and methods are provided for compressing data. A method may include receiving an input data block to be compressed, determining numbers of occurrences for distinct symbols in the input data block, generating reduced numbers of occurrences for the distinct symbols based on the numbers of occurrences for the distinct symbols and encoding the input data block using the reduced numbers of occurrences as probability distribution of the distinct symbols in the input data block.