Reduced Order Parasitic Circuit Model for Fast Simulation
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Solution Overview
Problem
Integrated circuit design faces challenges in efficiently simulating and optimizing circuit performance due to the large number of parasitic circuit elements, which results in long simulation times and high computational resource requirements, while simplifying these elements can compromise accuracy.
Innovation Solution
The development of a reduced order parasitic circuit element model that simulates circuit performance using fewer elements, allowing for faster simulation times while maintaining accuracy, by determining operational parameters through timing analysis and extraction of mask design data, and adjusting circuit elements to meet performance goals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full parasitic circuit element model is used for circuit simulation, then accuracy is maintained, but simulation time and computational resources increase significantly
Solution Approach 1:
The patent extracts only the critical parasitic elements that have significant impact on circuit performance, rather than including all parasitic elements. This selective extraction approach maintains simulation accuracy for key performance metrics while reducing the overall model complexity and simulation time.
Solution Approach 2:
The patent creates a simplified copy or representation of the full parasitic model by using equivalent circuit elements that replicate the dominant parasitic effects. This reduced-order model captures essential behavior without requiring complete fidelity to all physical parasitic elements.
2Productivity
If parasitic circuit elements are simplified to reduce simulation time, then computational resources are reduced, but accuracy is compromised
Solution Approach 1:
The patent applies different levels of model fidelity to different parts of the circuit based on their importance. Critical signal paths and high-impact parasitic elements are modeled with higher accuracy, while less significant elements use simplified representations, optimizing the balance between speed and accuracy.
Solution Approach 2:
The patent changes the parameter representation of parasitic elements from detailed physical models to simplified equivalent parameters. By transforming complex parasitic structures into equivalent circuit parameters (such as equivalent resistance, capacitance, and inductance values), the model becomes computationally efficient while preserving essential electrical behavior.
3Reliability
If iterative circuit optimization is performed with full accuracy modeling, then performance goals are reliably achieved, but computational resource requirements become prohibitive
Solution Approach 1:
The patent performs preliminary identification and extraction of dominant parasitic elements before the iterative optimization process begins. This upfront analysis creates a pre-characterized reduced-order model that can be used throughout subsequent optimization iterations, avoiding the need to re-analyze all parasitic elements in each iteration and thus reducing cumulative computational resource consumption.
Data Source
AI summary
A method for the simulation of a circuit is disclosed. The method may include the determination of parasitic circuit elements, and the determination of one or more operational parameters dependent upon at least the parasitic circuit elements. A model of the parasitic circuit elements may then be generated based upon the one or more operational parameters. The circuit may then be simulated using the model of the parasitic circuit elements to determine a performance level of the circuit. At least one active circuit element may be modified in response to determining that the performance level does not meet a goal.