Reduced Parity Data Management for Memory Sub-Systems
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Solution Overview
Problem
Current memory sub-systems face challenges in efficiently managing parity data, leading to performance issues and high storage requirements due to the need for extensive cache memory to handle multi-page and multi-plane parity protection, which affects user storage capacity and system performance.
Innovation Solution
The implementation of a reduced parity data management component that divides parity data into separate sets and uses an XOR operation to generate a reduced parity data set, which is written to the memory sub-system after a successful program operation, significantly reducing the storage space required for temporary parity data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive cache memory is used to handle multi-page and multi-plane parity protection, then data reliability is improved, but storage capacity and system performance deteriorate
Solution Approach 1:
The patent segments parity data into separate sets corresponding to different word lines, rather than using a single extensive cache for all parity data. This segmentation allows parity data to be distributed across multiple smaller storage locations, reducing the requirement for large contiguous cache memory while maintaining comprehensive parity protection for multi-page and multi-plane operations.
Solution Approach 2:
The patent organizes parity data along the word line dimension, creating a dimensional structure where parity data is associated with specific word lines rather than being stored in a monolithic cache. This dimensional organization reduces the storage capacity requirement by exploiting the structure of the memory device to distribute parity data across different word line locations.
2Reliability
If extensive cache memory is used to handle multi-page and multi-plane parity protection, then data reliability is improved, but system performance deteriorates
Solution Approach 1:
By segmenting parity data into word line-specific sets, the patent enables parallel processing of parity operations on different word lines. This segmentation reduces the performance bottleneck associated with accessing a single large cache memory, as parity data can be retrieved and processed from multiple distributed locations simultaneously, thereby improving overall system performance.
Solution Approach 2:
The patent performs parity data preparation and organization in advance, structuring it according to word line associations before actual write operations. This preliminary organization allows the system to quickly access and process parity data during operations without incurring large performance penalties, as the data is already positioned optimally for efficient retrieval and processing.
3Reliability
If parity data is stored for each word line, then error correction capability is improved, but storage space requirement increases
Solution Approach 1:
The patent divides parity data into separate sets for different word lines, with each set stored in association with its corresponding word line. This segmentation enables efficient error correction for each word line using its dedicated parity set, while avoiding the need to allocate storage space for complete parity data of all word lines simultaneously, thereby reducing overall storage space requirements.
Solution Approach 2:
The patent extracts and stores only the necessary parity data for each specific word line in its associated storage location, rather than storing all parity data in a centralized location. This extraction approach ensures that each word line has its required parity data readily available for error correction, while minimizing the total storage space by eliminating redundant parity data storage.
Data Source
AI summary
A method includes receiving, by a memory sub-system, host data to be written to a plurality of blocks of a memory device associated with a memory sub-system, where each of the plurality of blocks are coupled to one of a plurality of word lines of the memory device. The method can further include generating parity data for each word line of the block; dividing the parity data into one of either a first word line parity set or a second word line parity set; generating a reduced parity data set with exclusive or parity values for the first word line parity set and for the second word line parity set; and writing the reduced parity data set in the memory sub-system.