Reduced Pin Count Scan Chain Using Time-Multiplexed Signals
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Solution Overview
Problem
Small pin count packages in electronic circuitry face challenges in implementing scan chains due to the limited number of available pins, as traditional scan chain implementations require at least four pins for effective testing.
Innovation Solution
The implementation of a reduced pin count scan chain is achieved by combining scan signals such as ScanDataIn and ScanDataOut or ScanEnable with existing pins, using weak output drivers and additional circuitry to encode and decode signals, allowing the scan chain to operate with as few as two or three pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan chain implementation is used, then testability and test coverage are enhanced, but the number of required pins increases to at least four
Solution Approach 1:
The patent combines multiple scan chain signals (ScanDataIn, ScanDataOut, ScanEnable) onto fewer pins by using bidirectional pin operation and time-multiplexing. Specifically, ScanDataIn and ScanDataOut are merged on the same pin, and ScanEnable is merged with either ScanDataIn or ScanDataOut, reducing the pin count from four to two or three while maintaining scan chain functionality through careful signal timing and weak driver design.
Solution Approach 2:
The patent makes pins serve multiple functions: pins are used both as scan chain I/O and as weak drivers for signal output. The same pin that receives ScanDataIn also outputs ScanDataOut during different time periods, and the weak driver capability allows the pin to serve dual purposes without interfering with the primary scan chain operation. This multi-functionality reduces the total pin count required.
2Quantity of substance
If pins are combined to reduce pin count, then pin usage is minimized, but signal interference and driver conflicts may occur
Solution Approach 1:
The patent applies different driver strengths to different output paths: strong drivers are used for normal logic outputs, while weak drivers are used specifically for scan chain outputs on shared pins. This local differentiation in driver strength allows the weak driver to be easily overdriven by external test equipment when needed, while strong drivers maintain signal integrity for normal operation. The weak driver design specifically addresses the shared pin locations to prevent interference.
Solution Approach 2:
The patent uses time-multiplexing where pins alternate between different signal roles during different time periods. During test mode, pins switch between receiving ScanDataIn and outputting ScanDataOut in different clock cycles. This periodic switching of signal directions and functions on shared pins prevents simultaneous conflicting signal drives, eliminating driver conflicts while maintaining reduced pin count.
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AI summary
A synchronous logic device with reduced pin count scan chain includes more than two flip/flops (SDCO, SDC1, SDC2) coupled to form a shift register for receiving a scan data input signal (ScanDataln), a combinational logic circuit (20) for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal, a first multiplexer (MUX10) for providing a clock signal to the more than two flip/flops during a test mode, a second multiplexer (MUX12) for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit (20), and for providing a scan data output signal (ScanDataOut).