Reduced-Power Boost Circuit for Low Active Power Write Driver
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Solution Overview
Problem
The challenge in reducing power consumption in memory arrays, particularly in processors, is exacerbated by the increased capacitance of bit lines and the limited voltage differential under reduced supply voltage conditions, leading to inefficient writing performance and reliability issues.
Innovation Solution
A write driver with a reduced-power boost circuit is implemented, where a boost circuit is selectively coupled to the bit line circuit to drive it below ground voltage, independent of the write driver circuit, and activated only when the boost signal is active and the write data is in a logic low state, allowing for dynamic timing control and reducing the size and power consumption of the boost capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a boost circuit is integrated with the write driver circuit, then the write performance is improved, but the power consumption and circuit complexity increase
Solution Approach 1:
The patent divides the write driver into separate functional blocks: a write driver circuit and a distinct boost circuit. The write driver circuit contains only the necessary transistors for writing data, while the boost circuit is implemented as a separate entity with its own control logic. This segmentation allows each circuit to be optimized independently, reducing the overall power consumption while maintaining write performance.
Solution Approach 2:
The boost circuit is activated periodically or selectively based on the write operation requirements, rather than being continuously active. The control circuit enables the boost circuit only when needed to drive the bit line below ground potential, and disables it otherwise. This periodic activation reduces average power consumption while maintaining the ability to improve write performance when required.
2Reliability
If the boost capacitor size is increased to drive bit line below ground voltage, then the write reliability is improved, but the area and power consumption increase
Solution Approach 1:
The patent introduces a control circuit as an intermediary between the write driver circuit and the boost circuit. This control circuit manages the activation and deactivation of the boost circuit based on the write operation status, ensuring that the boost capacitor is only engaged when necessary. This intermediary control allows the system to achieve reliable writes below ground potential without requiring the boost capacitor to be permanently connected or oversized.
Solution Approach 2:
The patent dynamically changes the operational parameters of the boost circuit based on write requirements. The control circuit adjusts the timing and duration of boost circuit activation, and potentially the voltage levels, to achieve reliable bit line driving below ground potential while minimizing the required capacitor size and associated area.
3Productivity
If the write driver circuit is made larger to handle increased bit line capacitance, then the write performance is improved, but the power consumption and area increase
Solution Approach 1:
The patent segments the write driver functionality into two separate circuits: a compact write driver circuit that handles basic write operations, and a dedicated boost circuit that provides additional driving capability when needed. This segmentation allows the main write driver circuit to remain simple and low-power, while the boost circuit provides enhanced performance only during specific operations.
Solution Approach 2:
The patent implements dynamic control of the boost circuit through a control circuit that adjusts its activation based on real-time write operation requirements. This dynamic approach allows the system to scale its driving capability from minimal (normal operation) to maximum (boost mode) as needed, rather than maintaining a permanently large and complex write driver circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances write performance and reliability by reducing the size of the boost capacitor and write driver, leading to lower power consumption and improved operational efficiency in memory arrays.
Implementation Method 1
a boost circuit that is distinct from the write driver circuit, coupled directly to the bit line circuit without being coupled to discharge internal capacitance of the write driver circuit
Data Source
AI summary
Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.