Reduced-Power Memory With Per-Sector Power Control
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Solution Overview
Problem
The significant power consumption by memory arrays in processors leads to increased cooling costs, reduced battery life, and decreased reliability, particularly due to leakage currents and higher power usage during access operations compared to retention operations.
Innovation Solution
Implementing a reduced-power memory system with per-sector power/ground control and early address processing, where the memory is divided into sectors and sub-sectors, allowing for selective powering up of only the necessary sectors and sub-sectors based on address portions, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the entire memory array is kept powered up for fast access, then access speed is improved, but power consumption increases
Solution Approach 1:
The memory array is divided into multiple independently powerable sectors. Only the sector containing the requested data is powered up during access operations, while other sectors remain in a low-power state. This segmentation allows the system to maintain fast access speed for active sectors without powering up the entire memory array, thereby reducing overall power consumption.
Solution Approach 2:
The memory system performs preliminary power-up of the specific sector containing the requested data before the actual access operation. The sector is activated in advance based on address decoding, ensuring that when the access occurs, the data is immediately available without delay, thus maintaining fast access speed while avoiding the need to keep all sectors powered up continuously.
2Loss of time
If more memory sectors are kept active for faster data retrieval, then access time is reduced, but leakage current increases
Solution Approach 1:
The memory is segmented into multiple sectors with independent power control. This allows the system to activate only the specific sector containing the requested data rather than keeping multiple or all sectors active. By limiting the number of active sectors to the minimum necessary, leakage current is significantly reduced while access time remains fast for the active sector.
Solution Approach 2:
The power state of memory sectors is dynamically changed based on access requirements. Sectors transition between active and low-power states depending on whether they contain currently requested data. This parameter change allows the system to optimize the balance between access time and leakage current by adjusting the number of active sectors to match actual access needs.
Data Source
AI summary
A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector power/ground control and early address to advantageously reduce power consumption. Selective power control of sectors comprised in the reduced-power memory is responsive to a subset of address bits used to access the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via an increase of differential between power and ground levels from a retention differential to an access differential. Time needed to vary the differential is masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.