Reduced-Resolution Video Coding for Bit Rate and Prediction Balance

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Solution Overview

Problem

Existing video coding technologies face inefficiencies in reducing redundancy and bit rate requirements, particularly in intra prediction and motion compensation, due to the increasing complexity and bit usage for less likely prediction directions and motion vectors.

Innovation Solution

The proposed solution involves reduced-resolution coding techniques, where blocks are down-sampled to generate reduced-resolution prediction and reconstruction blocks, and then up-sampled to full resolution, along with scaled motion vectors and affine parameters, to optimize video decoding and encoding processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If reduced-resolution coding is applied to current blocks, then bit rate is reduced and coding efficiency is improved, but motion vector accuracy and prediction precision may deteriorate

Engineering Contradiction:
Improvebit rateVSAvoidprediction precision
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The video sequence is segmented into different resolution levels. Current blocks are coded at reduced resolution while reference blocks maintain full resolution, creating a multi-resolution coding structure that balances bit rate reduction with prediction accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The resolution parameter is dynamically changed based on block characteristics. A block level flag indicates whether reduced-resolution coding is applied, allowing adaptive parameter adjustment to optimize the trade-off between compression efficiency and prediction precision

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If down-sampling is used to generate reduced-resolution prediction blocks, then computational complexity is reduced, but reconstruction accuracy may be degraded

Engineering Contradiction:
Improvecomputational complexityVSAvoidreconstruction accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

Down-sampling is performed as a preliminary step before prediction coding. Full-resolution reference blocks are down-sampled to generate reduced-resolution prediction blocks, which are then up-sampled and combined with residuals to achieve accurate reconstruction without full-resolution processing throughout

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Reduc-resolution blocks serve as an intermediary representation. The system uses reduced-resolution prediction blocks as intermediaries that are subsequently refined through up-sampling and residual addition to achieve final high-quality reconstruction

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If motion vectors are scaled for reduced-resolution blocks, then bit rate is reduced, but motion compensation accuracy may deteriorate

Engineering Contradiction:
Improvebit rateVSAvoidmotion compensation accuracy
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

Different quality levels are applied to different parts of the motion compensation process. Motion vectors are scaled to reduced resolution for coding efficiency, while the final motion compensation is performed at full resolution using up-sampled reference blocks and scaled motion vectors to maintain local accuracy where needed

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP4088474B1Method and apparatus for video coding
Publication Date: 2026.04.15 TENCENT AMERICA LLC
  • EP4088474B1 patent drawingFigure 1A
  • EP4088474B1 patent drawingFigure 1B
  • EP4088474B1 patent drawingFigure 1C

AI summary

Aspects of the disclosure include methods, apparatuses, and non-transitory computer-readable storage mediums for video encoding/decoding. An apparatus includes processing circuitry that decodes a video bitstream to obtain a reduced-resolution residual block for a current block. The processing circuitry determines that a block level flag is set to a pre-defined value. The pre-defined value indicates that the current block is coded in reduced-resolution coding. Based on the block level flag, the processing circuitry generates a reduced-resolution prediction block for the current block by down-sampling a full-resolution reference block of the current block. The processing circuitry generates a reduced-resolution reconstruction block for the current block based on the reduced-resolution prediction block and the reduced-resolution residual block. The processing circuitry generates a full-resolution reconstruction block for the current block by up-sampling the reduced-resolution reconstruction block.