Reduced Scan Chains for IC Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Sequential scan techniques for testing integrated circuits often result in increased test time, power dissipation, and cost due to the use of multiple memory elements in scan chains, which are not all contributing to fault determination.
Innovation Solution
The solution involves forming scan chains with a reduced number of memory elements that are strategically selected to cover both intra- and inter-portion testing, using memory elements connected to interface logic for comprehensive testing, thereby reducing the length of scan chains and optimizing test time, power consumption, and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple memory elements are used in scan chains for comprehensive testing, then testing coverage is improved, but test time increases
Solution Approach 1:
The patent extracts only the essential memory elements that are actually needed for fault detection from the complete set of memory elements in the circuit. By identifying and removing non-essential memory elements from scan chains, the test time is reduced while maintaining adequate testing coverage for the critical portions of the circuit.
Solution Approach 2:
The patent divides the circuit into multiple portions and creates separate scan chains for each portion, focusing on testing only the essential memory elements within each segment. This segmentation allows comprehensive testing of critical areas without requiring all memory elements to be included in every scan chain, thereby reducing overall test time.
2Reliability
If multiple memory elements are used in scan chains for comprehensive testing, then testing coverage is improved, but power dissipation increases
Solution Approach 1:
The patent extracts only the essential memory elements needed for fault detection from the complete set of memory elements. By excluding non-essential memory elements from scan chains, the number of active elements during testing is reduced, which directly lowers power dissipation while maintaining adequate testing coverage.
3Reliability
If multiple memory elements are used in scan chains for comprehensive testing, then testing coverage is improved, but testing cost increases
Solution Approach 1:
The patent extracts only the essential memory elements required for effective fault detection, eliminating the need to include all memory elements in scan chains. This reduction in scan chain complexity decreases the complexity of test pattern generation and reduces testing costs while maintaining adequate coverage of critical circuit portions.
Data Source
AI summary
Each portion of an integrated circuit is tested using Automatic test pattern generation (ATPG) technique to detect intra-portion faults. Inter-portion faults are detected by first forming a scan chain containing (a) the memory elements in the fan-out of the inputs to each of said plurality of portions, (b) the memory elements in the fan-in of the outputs of each of said plurality of portions, (c) memory elements connected to combinatorial logic propagating data inputs to the memory elements of (a), and (d) memory elements connected to provide control signals to (a), (b) and (c). Sequential scan tests are then performed on the scan chain thus formed.