Reduced-State Maximum Likelihood Decoding for CPM Signals
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Solution Overview
Problem
Current communication systems face challenges with high computational complexity in Forward Error Correction (FEC) schemes, particularly at higher modem data rates, due to limitations in commercially available digital signal processors (DSPs) and Field Programmable Gate Array (FPGA) technology, which hinder efficient decoding of convolutional codes and continuous phase modulation signals.
Innovation Solution
A reduced-state maximum likelihood decoder is developed, featuring programmable trellis parameters and a generic, programmable architecture that supports demodulation of waveforms with memory, including Continuous Phase Modulation (CPM), using a Ungerboeck-style set-partitioning algorithm to reduce the complexity of the trellis structure and implement decision feedback for improved error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a maximum likelihood decoder (Viterbi Algorithm) is used for FEC decoding, then error correction capability is improved, but computational complexity increases significantly
Solution Approach 1:
The patent segments the trellis structure into multiple stages with a reduced number of states at each stage. Instead of processing all possible states in a full Viterbi decoder, the invention divides the state space and processes segments independently, reducing the computational burden while maintaining error correction capability through the segmented processing approach.
Solution Approach 2:
The patent applies partial action by implementing a reduced-state Viterbi algorithm that processes only a subset of the full state space. By using a reduced number of states (e.g., 4-state or 8-state trellis instead of full-rate trellis), the decoder performs partial decoding that suffices for many practical applications, significantly reducing complexity while providing adequate error correction for typical channel conditions.
2Reliability
If stronger FEC codes are used to approach the Shannon limit, then error correction performance is improved, but decoding complexity increases
Solution Approach 1:
The patent changes the parameter of the trellis structure by using a reduced number of states and modified transition rules. Instead of implementing strong codes with full-rate trellises that have many states, the invention modifies the trellis parameters (number of states, transition probabilities, branch metrics) to achieve a balance between error correction performance and decoding complexity, making strong codes practical for implementation.
3Productivity
If higher data rates are implemented, then communication throughput is improved, but computational complexity of FEC schemes becomes prohibitive
Solution Approach 1:
The patent introduces dynamics by making the trellis structure adaptable to different data rates and channel conditions. The reduced-state Viterbi decoder can dynamically adjust its operation based on the required data rate, selecting appropriate trellis configurations and processing depths to maintain computational feasibility while supporting higher throughput requirements.
Data Source
AI summary
A decoder includes at least one programming input for a plurality of programmable reduced-state trellis parameters. A programmable device is connected to the at least one programming input and implements a reduced-state maximum likelihood decoder that is operable for processing a continuous phase modulated (CPM) signal and returning up to N bits that were transmitted based on a maximum likelihood and current winning super-state and corresponding survivor full-state. The programmable device calculates the path metrics for every super-state and determines a best path based on the reduced-state trellis parameters.