Reduced State Quadbit Flash Memory Cell Design
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Solution Overview
Problem
Multi-level flash memory devices face challenges in maintaining narrow threshold voltage (Vt) distributions and read margins, especially as device features shrink and memory cell density increases, leading to complementary bit disturb (CBD) issues that affect data accuracy and storage capacity.
Innovation Solution
A reduced state multi-level flash memory device and method that restricts certain program pattern combinations by limiting the maximum allowable difference between program and erase threshold voltages, eliminating worse-case CBD voltage patterns, and varying programming gate and drain voltages to achieve improved read margins and CBD control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level flash memory devices increase device features shrink and memory cell density, then storage capacity is improved, but complementary bit disturb (CBD) issues worsen affecting data accuracy
Solution Approach 1:
The patent applies parameter changes by restricting program pattern combinations and limiting the maximum allowable difference between program and erase threshold voltages. This controls the electrical parameters during programming to prevent excessive threshold voltage shifts that cause CBD, thereby maintaining data accuracy while supporting higher density.
Solution Approach 2:
The patent implements dynamic voltage adjustment by varying programming gate and drain voltages based on the specific program pattern being written. This dynamic control adapts the programming conditions to minimize CBD effects for different data patterns, resolving the contradiction between high density and data accuracy.
2Quantity of substance
If multi-level flash memory devices increase device features shrink and memory cell density, then storage capacity is improved, but threshold voltage distribution width increases
Solution Approach 1:
The patent uses parameter changes to limit the threshold voltage spread by constraining program pattern combinations and controlling the difference between program and erase voltages. This ensures that even as density increases, the threshold voltage distributions remain narrow and well-defined.
Solution Approach 2:
The patent applies partial action by not using all possible program pattern combinations. Instead of programming all 16 possible states, it restricts to subsets that maintain narrow Vt distributions, accepting reduced programming flexibility to achieve better voltage distribution control.
3Quantity of substance
If multi-level flash memory devices use all possible program pattern combinations, then storage capacity is maximized, but read margins deteriorate
Solution Approach 1:
The patent implements partial action by selecting only beneficial program pattern combinations for multi-level programming. This restricted set of patterns maintains adequate read margins between different data states while still achieving multi-bit storage per cell, resolving the contradiction between capacity and read accuracy.
Solution Approach 2:
The patent changes the programming parameters by imposing constraints on program patterns and voltage differences. This ensures that programmed states maintain sufficient separation in threshold voltage, preserving read margins even as multiple bits are stored in each cell.
4Speed
If multi-level flash memory devices program with high threshold voltage difference, then programming speed is improved, but charge loss increases
Solution Approach 1:
The patent applies parameter changes by limiting the maximum allowable difference between program and erase threshold voltages. This controls the programming voltage parameters to achieve sufficient programming speed while preventing excessive charge loss that would occur with larger voltage differences.
Solution Approach 2:
The patent uses dynamic voltage adjustment, varying the programming gate and drain voltages based on the specific program pattern. This dynamic approach optimizes programming speed for each pattern while minimizing charge loss, avoiding the need to use consistently high voltages that would cause excessive charge loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves highly compact Vt distributions, reduced charge loss, and improved data retention, enhancing the reliability and performance of multi-level flash memory cells while maintaining adequate read margins and reducing CBD effects.
Implementation Method 1
The cells are generally programmed by hot electron injection and erased by Fowler-Nordheim tunneling or other mechanisms.
Implementation Method 2
The cells are generally programmed by hot electron injection and erased by Fowler-Nordheim tunneling or other mechanisms.
Data Source
AI summary
A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.