Reduced Voltage Flash Memory Architecture for Embedded Power
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Solution Overview
Problem
Conventional flash memory technologies require high voltages for read operations, leading to increased power consumption and chip size, and may experience reduced operating speed due to series resistance from multiple transistors per bitline, which is not suitable for embedded systems with real-time computing constraints.
Innovation Solution
The development of reduced-voltage nonvolatile flash memory with n transistors per bitline, where n is greater than or equal to 4, featuring a stacked gate structure and eliminating the need for a charge pump by using a voltage regulator to reduce voltage levels, allowing for lower voltage write signals and pass gate voltages below the operating voltage, thus reducing power consumption and chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory uses multiple transistors per bitline (2Tr or 3Tr configuration), then data protection against programming disturbances is improved, but operating speed deteriorates due to series resistance
Solution Approach 1:
The patent extracts the select gate transistor from the bitline series path by implementing a source-side select gate configuration. The select gate is moved to the source side of the memory cell, allowing it to control access without adding series resistance to the bitline current path, thus maintaining both data protection and high operating speed
Solution Approach 2:
The patent introduces a source-side select gate as an intermediary element that mediates between the bitline and memory cell. This select gate controls memory cell access through the source terminal rather than the bitline, eliminating the trade-off between protection and speed by placing the control function outside the critical current path
2Power
If flash memory uses high voltage for read operations, then programming capability is improved, but power consumption increases
Solution Approach 1:
The patent changes the voltage parameter by implementing a voltage regulator that converts a single low supply voltage into the multiple voltage levels needed for different operations. Read operations use low voltage to minimize power consumption, while write operations dynamically generate high voltage only when needed, thus achieving both programming capability and low power consumption
Solution Approach 2:
The patent introduces dynamic voltage generation through a charge pump that activates only during write operations. During read operations, the system operates at low voltage for minimal power consumption, while during write operations, the charge pump dynamically generates high voltage to enable programming, thus adapting power consumption to operational requirements
3Power
If flash memory includes charge pump circuitry for voltage generation, then programming capability is improved, but chip size increases
Solution Approach 1:
The patent merges the charge pump circuitry with the voltage regulator into an integrated voltage generation unit. This combined circuit generates both the high voltage needed for programming and the regulated low voltage for reading, eliminating the need for separate voltage generation circuits and reducing overall chip size while maintaining full programming capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient operation with lower voltages, reduced power consumption, and faster access speeds, making it suitable for embedded systems by maintaining programmed threshold voltages below the supply voltage, thereby avoiding the need for charge pumps and enhancing performance in embedded applications.
Implementation Method 1
reducing a power supply voltage to a lower write signal voltage
Implementation Method 2
one memory cell transistor may be sandwiched between two select gate transistors
Data Source
AI summary
Systems include a first semiconductor die comprising a charge pump to generate power supply signals, a second semiconductor die comprising a memory array and programming circuitry, and a bus connected to the first and second semiconductor dies to carry the power supply signals to the programming circuitry. The programming circuitry is adapted to program memory cells of the memory array to respective threshold voltages that are each less than or equal to the first voltage.