Reduced Volume Interconnect for 3D Chip Stack Height
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Solution Overview
Problem
Conventional solder deposition methods for 3D chip stacking are expensive, complex, and limit alloy options, resulting in increased package height and inadequate performance for high-frequency signals due to substantial standoff height between chips.
Innovation Solution
A method involving the formation of reduced volume conductive structures with a specific volume configuration and alignment on under bump metallurgy pads, allowing for metallurgical bonding between silicon layers to minimize interconnect gap, utilizing lead-free solder alloys that form intermetallic compounds with high thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional solder deposition methods are used, then electrical connection between chips is achieved, but the standoff height substantially increases the overall package height
Solution Approach 1:
The patent changes the volume parameter of the conductive structure from conventional sizes to reduced volumes (e.g., diameter ratio of unreflowed diameter to pad diameter of about one-third-to-one or less). This parameter change enables the conductive structure to collapse during reflow, reducing the interconnect gap and overall package height while maintaining electrical connection reliability through proper metallurgical bonding.
Solution Approach 2:
The patent utilizes the phase transition of the conductive material from solid to liquid during reflow heating, and back to solid upon cooling. The reduced volume conductive structure is designed to collapse during the liquid phase, reducing the interconnect gap, and then solidifies to maintain the reduced height configuration, achieving both height reduction and reliable electrical connection.
2Ease of manufacture
If conventional solder deposition methods are used, then electrical connection is established, but the process is expensive and complex with limited alloy options
Solution Approach 1:
The patent extracts the complexity and limitations of conventional solder deposition methods by using a simplified transfer and collapse process. This extraction enables the use of various lead-free solder alloys without requiring complex deposition equipment, as the process relies on transfer and thermal collapse rather than precise deposition control, thereby improving ease of manufacture and alloy versatility.
Solution Approach 2:
The reduced volume conductive structure design serves multiple functions: it provides electrical connection, enables height reduction through collapse, supports various lead-free alloys, and facilitates metallurgical bonding. This multi-functionality improves ease of manufacture by consolidating multiple requirements into a single structural design that works across different alloy compositions.
3Length of stationary object
If reduced volume conductive structures are used, then interconnect gap is reduced, but the volume of conductive material is minimized
Solution Approach 1:
The patent exploits the phase transition of conductive material during reflow to achieve interconnect gap reduction with minimal material volume. The reduced volume conductive structure is designed to collapse during the liquid phase, and the phase change enables this collapse without requiring additional material, as the material redistributes during melting and solidifies in the collapsed configuration.
Solution Approach 2:
The patent changes the volume parameter of the conductive structure to a reduced level (diameter ratio of about one-third-to-one or less), which enables the structure to collapse during reflow and reduce the interconnect gap. This parameter change optimizes the balance between having sufficient conductive material for reliable electrical connection and minimizing the interconnect gap for reduced package height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall height of the chip stack, enhances power efficiency, increases bandwidth, and lowers costs while supporting high-frequency signal transmission with improved thermal and electrical characteristics.
Implementation Method 1
heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers
Implementation Method 2
a percentage of intermetallic compounds in a junction between the conductive structure and corresponding aligned under bump metallurgy (UBM) pads
Implementation Method 3
at least a given one of the conductive structures between aligned electrical contact locations on corresponding adjacent silicon layers collapses to reduce an interconnect gap therebetween
Implementation Method 4
heating the interconnect so as to metallurgically bond... in such a manner that at least a given one of the conductive structures... collapses
Data Source
AI summary
A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.