Redundancy Circuit Merging Fuse Blocks for Memory Yield
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Solution Overview
Problem
The increasing integration of semiconductor memory apparatuses leads to inefficiencies in manufacturing yield and cost due to the need for multiple redundancy cells and fuse blocks, which occupy significant area and impede miniaturization, as existing redundancy circuits require multiple components to handle multiple repaired addresses.
Innovation Solution
A redundancy circuit design that shares a comparison unit and uses dual fuse enable units and determination units to handle information of multiple repaired addresses using a single comparison unit, reducing the overall area occupied and enabling miniaturization by efficiently managing redundancy information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple fuse blocks are used to handle multiple repaired addresses, then the number of replaceable failed cells increases, but the area occupied by redundancy circuits increases
Solution Approach 1:
The patent merges multiple fuse blocks into a single integrated redundancy circuit. The comparison unit receives a comparison address and compares it with multiple stored repaired addresses simultaneously, eliminating the need for separate fuse blocks for each repaired address. This consolidation maintains the ability to handle multiple repaired addresses while significantly reducing the area occupied by redundancy circuits.
Solution Approach 2:
The comparison unit is designed with multi-functionality to compare the comparison address with multiple stored repaired addresses in one operation. Instead of requiring separate comparison units and fuse blocks for each repaired address, a single comparison unit performs multiple comparison functions, thereby reducing the overall circuit area while maintaining the capability to replace multiple failed cells.
2Productivity
If the number of fuse blocks increases to replace more failed cells, then manufacturing yield improves, but device miniaturization is impeded
Solution Approach 1:
The patent combines multiple fuse blocks into one integrated redundancy circuit structure. The comparison unit stores multiple repaired addresses and performs comparisons in a single operation, eliminating the need for multiple separate fuse blocks. This merging approach increases manufacturing yield by enabling replacement of multiple failed cells while minimizing the chip area required, thus supporting device miniaturization.
3Manufacturing precision
If separate fuse blocks are used for each repaired address, then address repair accuracy is maintained, but circuit complexity increases
Solution Approach 1:
The comparison unit is designed to perform multiple comparison operations simultaneously, comparing the comparison address with multiple stored repaired addresses in one process. This multi-functional design maintains address repair accuracy by ensuring precise comparison with all relevant repaired addresses, while reducing circuit complexity by eliminating the need for separate fuse blocks and comparison units for each repaired address.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for the effective conversion of semiconductor memory apparatuses with failed cells into functional products while minimizing the area required for redundancy circuits, thereby enhancing manufacturing efficiency and supporting the miniaturization of semiconductor memory apparatuses.
Implementation Method 1
By conducting a fuse cutting process, in which a specified fuse among a plurality of fuses is cut using laser, the address information of a repaired cell may be recorded.
Data Source
AI summary
In one embodiment, a redundancy circuit may include a comparison unit configured to record a first repair address through fuse cutting, compare a comparison address with the first repair address, and output a comparison result signal; a first fuse enable unit configured to output a first fuse enable signal for repairing the first repair address; a second fuse enable unit configured to output a second fuse enable signal for repairing a second repair address; a first determination unit configured to output a first repair determination signal in response to receipt of the first fuse enable signal and the comparison result signal; and a second determination unit configured to output a second repair determination signal in response to receipt of an inverted signal of a value of the comparison result signal corresponding to the certain bit, remaining bits, and the second fuse enable signal.