Redundancy Code Path Synchronization for Low-Latency Fault Detection
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Solution Overview
Problem
Existing hardware fault detection methods in safety-critical areas, such as automotive and medical, result in increased latency and compromise the performance-power-area (PPA) trade-off, limiting computational performance.
Innovation Solution
A synchronous digital network with a redundancy code path and a redundancy code generation unit that adds redundancy codes to the signal path, allowing for fault detection without blocking the signal path, and includes a delay unit to synchronize the redundancy code path with the signal path, enhancing diagnostic coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block codes (e.g., Hamming code) are applied synchronously with the signal flow for fault detection, then fault detection capability is improved, but latency increases and maximum clock frequency decreases
Solution Approach 1:
The patent divides the fault detection process into separate asynchronous stages: code generation occurs independently from the main signal path, and fault determination happens in a separate comparison stage. This segmentation allows the redundancy code to be generated without blocking the critical signal path, thereby maintaining high clock frequencies while still providing comprehensive fault detection capability.
Solution Approach 2:
The redundancy code is generated in advance as a separate parallel process before the fault determination stage. By preparing the redundancy code independently and asynchronously, the system eliminates the need to wait for code generation during the critical signal path operation, thus reducing latency without sacrificing fault detection effectiveness.
2Reliability
If block codes are applied synchronously with the signal flow, then fault detection capability is improved, but system performance decreases
Solution Approach 1:
The patent segments the processing into independent parallel paths: the main signal path operates at full speed without interruption, while the redundancy code generation and fault determination occur in separate asynchronous stages. This segmentation ensures that fault detection functionality is added without degrading the performance of the critical signal path.
Solution Approach 2:
The patent introduces an intermediary asynchronous timing mechanism that mediates between the fast signal path and the fault detection process. This intermediary allows the redundancy code to be generated and compared without directly interfering with the timing-critical signal path, thereby maintaining high system performance while enabling comprehensive fault detection.
3Reliability
If redundancy code path is added for fault detection, then diagnostic coverage is improved, but device complexity increases
Solution Approach 1:
The patent segments the redundancy system into modular functional blocks: a code generation unit, a delay unit for timing alignment, and a determination unit for fault analysis. This modular segmentation allows each component to be optimized independently and integrated into the existing system with minimal disruption, reducing the overall complexity increase compared to a monolithic approach.
Solution Approach 2:
The determination unit serves multiple functions: it compares the original signal with the redundancy code, detects faults, and provides diagnostic information. By making this unit multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while maintaining high diagnostic coverage.
Data Source
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AI summary
The present disclosure relates to a processing system, in particular a synchronous digital network, comprising a signal path and a redundancy code path, wherein the redundancy code path is an at least partially redundant path with respect to the signal path, a redundancy code generation unit located in the redundancy code path and configured to generate a redundancy code signal, a delay unit located in the redundancy code path, wherein a delay is applied to the redundancy code signal, and at least one redundancy code determination unit configured to determine a fault in the signal path and/or in the redundancy code path based on an output of the signal path and an output of the redundancy code path. The disclosure also relates to a corresponding method.