Redundancy Control Circuit for DRAM Refresh Accuracy
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Solution Overview
Problem
In semiconductor memory devices like DRAM, it is challenging to control the refresh operation of redundancy word lines effectively, leading to potential refresh operations on defective redundancy word lines, which is undesirable.
Innovation Solution
A redundancy control circuit and detection circuit system that uses anti-fuse arrays to identify defective word lines and redundancy word lines, generating status signals to prevent refresh operations on defective lines by selectively activating refresh stop signals based on match signals and enable bits stored in register circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If all redundancy word lines are refreshed regardless of their usage status, then the refresh operation is simplified, but defective redundancy word lines may be refreshed causing errors
Solution Approach 1:
The patent applies preliminary action by pre-storing the address of defective redundancy word lines in an anti-fuse array before the refresh operation occurs. During refresh, the detection circuit compares the current refresh address against these pre-stored defective addresses and generates a refresh stop signal when a match is detected, preventing refresh of defective lines before errors can occur.
Solution Approach 2:
The patent introduces an intermediary detection circuit and control signal mechanism between the refresh operation and the redundancy word lines. The detection circuit acts as a mediator that intercepts refresh operations, compares addresses, and selectively blocks refresh signals for defective lines while allowing normal lines to be refreshed, thus resolving the contradiction between simple operation and accurate control.
2Reliability
If redundancy word lines are selectively refreshed based on defect status, then refresh accuracy is improved, but the control system becomes more complex
Solution Approach 1:
The patent uses copying by storing the defective word line address in the anti-fuse array, creating a permanent record copy of the defect information. The detection circuit then copies this stored address information during each refresh cycle and compares it with the current refresh address, enabling selective refresh control without requiring complex real-time defect detection logic.
Solution Approach 2:
The patent replaces complex mechanical or logical control mechanisms with a simpler address comparison mechanism. Instead of using complex control logic to determine which redundancy lines need refreshing, the system substitutes this with a straightforward address matching process using the anti-fuse array and detection circuit, reducing overall control complexity while maintaining accuracy.
Data Source
AI summary
Disclosed herein is an apparatus that includes first register circuits configured to store a first address, and a comparing circuit configured to compare the first address with a second address. The comparing circuit includes first and second circuit sections. In a first operation mode, the comparing circuit is configured to activate a match signal when the first circuit section detects that the first bit group of the first address matches with the third bit group of the second address and the second circuit section detects that the second bit group of the first address matches with the fourth bit group of the second address. In a second operation mode, the comparing circuit is configured to activate the match signal when the first circuit section detects that the first bit group matches with the third bit group regardless of the second and fourth bit groups.