Redundancy Control System Error Detection via Algorithm Verification

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Solution Overview

Problem

In redundancy control systems, existing methods fail to accurately detect errors in computational data transmitted from redundant processing devices, leading to incorrect data recognition and inability to distinguish between verified and unverified data, especially when one processing device fails.

Innovation Solution

A redundancy control system that employs two processing devices generating data using different algorithms, comparing and verifying the data, and transmitting signature data for authentication, allowing error detection and fault diagnosis at the receiving end.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If CRC computation device is used for error detection in transmitted data, then transmission errors can be detected at receiving end, but inability to confirm correctness of computational data generated by redundant processing devices

Engineering Contradiction:
Improveerror detection capabilityVSAvoidinformation about processing device correctness
Core Design Contradiction:
Measurement precisionVSLoss of information

Solution Approach 1:

The patent introduces an intermediary verification mechanism where the receiving end uses stored generation algorithms to independently verify the computational data. This intermediary verification process bridges the gap between simple CRC error detection and comprehensive processing device correctness confirmation, allowing the system to detect both transmission errors and processing device failures without requiring direct communication between processing devices.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If redundant processing devices are used to generate computational data, then system reliability is improved, but inability to detect failure of processing devices when one system fails

Engineering Contradiction:
Improvesystem reliabilityVSAvoidprocessing device failure detection
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements a feedback mechanism where the receiving end verifies the computational data by regenerating it using stored algorithms and comparing it with the received data. This feedback loop provides continuous monitoring of processing device correctness, enabling detection of processing device failures while maintaining system redundancy. The verification result feeds back to confirm whether the redundant processing devices are functioning correctly.

Inventive Principle:
Principle #23Feedback

3Speed

If computational data is transmitted directly from processing device without verification, then transmission speed is maintained, but erroneous data may be wrongly recognized as correct

Engineering Contradiction:
Improvedata transmission speedVSAvoiddata correctness
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by having the receiving end prepare and store the generation algorithms in advance, so that verification can be performed immediately upon data receipt without delaying transmission. This preliminary preparation enables fast verification that maintains transmission speed while ensuring data correctness through algorithm-based validation of computational data.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8762788B2Redundancy control system and method of transmitting computational data thereof for detection of transmission errors and failure diagnosis
Publication Date: 2014.06.24 KK TOSHIBA
  • US8762788B2 patent drawing
  • US8762788B2 patent drawing
  • US8762788B2 patent drawing

AI summary

A redundancy control system and method of transmitting computational data are provided, for detection of transmission errors and failure diagnosis, including generating first computational data and generating first generated data using a first generation algorithm for error detection; generating second computational data and generating second generated data using a second generation algorithm for error detection; comparing the first/second computational data; transmitting transmission data including coincident computational data and the first/second generated data; generating, in the receiving device, computational data and third/fourth generated data from preset first/second generation algorithms; and comparing the first/third generated data and the first/third generated data, and detecting the presence or absence of an error in the received computational data.