Redundancy-Based Error Detection in Memory Devices
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Solution Overview
Problem
Memory devices face challenges in detecting and classifying errors, particularly those exceeding the threshold quantity detectable by on-device error correction techniques like ECC, which limits their ability to ensure data integrity in high-reliability applications.
Innovation Solution
Implementing redundancy-based error detection by storing redundant copies of codewords and generating error information bits to determine the error status, including error detection bits, data match bits, and parity match bits, allowing for the classification of errors beyond the ECC power without increasing ECC overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If on-device error correction techniques like ECC are used to detect errors, then error detection capability is improved up to a threshold quantity, but the ability to detect and classify errors exceeding the ECC power is lost
Solution Approach 1:
The patent segments the error detection task into multiple independent components: ECC decoding for basic error correction, separate syndrome bit generation for each codeword copy, and comparison logic for error classification. This segmentation allows the system to handle errors beyond ECC power by distributing detection functions across multiple parallel paths rather than relying on a single threshold-based mechanism.
Solution Approach 2:
The patent stores redundant copies of codewords in the memory array and generates corresponding syndrome bits for each copy. By maintaining multiple identical copies and their associated syndrome information, the system can compare results across copies to detect and classify errors that exceed the capability of individual ECC decoders, thereby extending error detection beyond the original ECC power threshold.
2Reliability
If redundant copies of codewords are stored to enable error detection beyond ECC power, then error classification capability is improved, but storage overhead increases
Solution Approach 1:
The patent implements redundancy by storing multiple copies of codewords and their associated syndrome bits in the memory array. This copying approach enables error classification beyond ECC power while maintaining a structured overhead that can be managed through efficient memory organization and access patterns.
Solution Approach 2:
The redundant storage structure serves multiple functions simultaneously: it provides error detection beyond ECC power, enables error classification, supports syndrome bit comparison, and maintains data integrity. This multi-functionality reduces the effective overhead by making the redundant storage serve several purposes rather than requiring separate mechanisms for each function.
3Measurement precision
If multiple codeword copies and syndrome bits are stored for enhanced error detection, then error status determination accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the error detection system into segmented functional units: individual ECC decoders for each codeword copy, separate syndrome bit generation circuits, and comparison logic that processes syndrome bits from multiple copies. This segmentation allows each component to remain relatively simple while the collective system achieves high error status determination accuracy through coordinated operation of the segments.
4Measurement precision
If on-device error correction techniques are used, then error detection is improved up to ECC power, but error classification for errors in excess of ECC power is not supported
Solution Approach 1:
The patent introduces syndrome bits as an intermediary mechanism that bridges ECC decoding and error classification. The syndrome bits carry error information from multiple codeword copies to a comparison unit, enabling the system to classify errors beyond ECC power without requiring the ECC decoder itself to perform classification functions. This intermediary layer adds versatility while preserving the precision of ECC-based detection.
Data Source
AI summary
Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.