Redundancy Selector Circuit for Non-Volatile Memory
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Solution Overview
Problem
Existing redundancy circuits in memory devices often fail to timely recognize defective memory cells due to operating speed issues, leading to incorrect selection of defective cells instead of redundant ones, which can result in reduced reliability and slower operating speeds.
Innovation Solution
A redundancy selector circuit that includes a ROM cell array for storing defective addresses, a ROM controller for selecting rows, a sense amplifier for sensing data bits, a latch block for serially receiving and latching defective address data, and a comparator block for detecting matching addresses during normal operation, allowing for timely activation of redundant cells and preventing read/program errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of the memory device is increased, then productivity is improved, but the reliability deteriorates because the redundancy checking circuit fails to timely recognize defective memory cells
Solution Approach 1:
The patent applies preliminary action by pre-loading defective address information into latch circuits before the actual memory access operation. The ROM controller sequentially selects rows of the ROM cell array during a setup phase, and the sense amplifier block senses data bits representing defective addresses in advance. This allows the redundancy checking circuit to be ready to immediately compare incoming addresses with stored defective addresses during high-speed operation, resolving the timing conflict between fast operation and reliable defect detection.
2Reliability
If longer set-up times are used to ensure proper operation of the redundancy checking circuit, then reliability is improved, but the overall operating speed of the memory device is reduced
Solution Approach 1:
The patent performs the address comparison operation in advance by loading defective addresses into latch circuits during a setup phase before normal memory operations begin. The ROM controller sequentially activates rows, and the sense amplifier block senses defective address data bits ahead of time. This preliminary preparation eliminates the need for extended set-up times during actual high-speed memory access, allowing the system to maintain both high reliability and fast operating speed.
3Productivity
If the redundancy checking circuit operates at high speed, then productivity is improved, but defective memory cells may be incorrectly selected instead of functional redundant memory cells
Solution Approach 1:
The patent performs address comparison in advance by pre-loading defective addresses into latch circuits before normal memory operations. The ROM controller sequentially selects rows during setup, and the sense amplifier block senses defective address data bits ahead of time. This preliminary comparison preparation ensures that when high-speed operations occur, the redundancy checking circuit already has the reference defective addresses ready, enabling accurate matching without sacrificing speed or precision.
Data Source
AI summary
A redundancy selector circuit for use in a non-volatile memory device include a ROM cell array, in which defective addresses are stored, including a plurality of ROM cells arranged in a matrix of rows and columns; a ROM controller for sequentially selecting rows of the ROM cell array at power-up; a sense amplifier block for sensing and amplifying data bits from ROM cells of the respective rows selected sequentially according to the control of the ROM controller; a latch block for receiving data bits sensed by the sense amplifier block through a switch circuit and latching the input data bits as a defective address; and a comparator block for detecting whether an address input in a normal operation matches one of the defective addresses stored in the latch block. As the rows are sequentially selected, the defective addresses of the ROM cell array are transferred to the latch block through the sense amplifier block by means of serial transfer.