Redundant A/D Converter Array Configuration for Higher Chip Yield
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Solution Overview
Problem
The manufacturing yield of semiconductor chips with aggregated A/D converters decreases as the number of converters increases due to the high likelihood of parameter failures, causing entire chips to be discarded if any parameter fails to meet specifications.
Innovation Solution
Incorporating redundant A/D converter circuits on a single semiconductor chip, with a control circuit to temporarily test and configure switches to connect only 'good' converters to signal paths, ensuring that the number of 'bad' converters does not exceed the number of redundant ones, thereby allowing the chip to be wired as a 'good' chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of A/D converters on a single chip is increased, then the processing capability and imaging quality are improved, but the manufacturing yield decreases due to increased likelihood of parameter failures
Solution Approach 1:
The patent applies preliminary action by testing and identifying functional A/D converters before final chip assembly. The system performs early characterization of each A/D converter's performance parameters, stores the results in a lookup table, and pre-determines which converters are functional. This allows the chip to be configured optimally before committing to a final design, thereby improving manufacturing yield while maintaining high processing capability.
Solution Approach 2:
The patent implements dynamics by making the chip configuration adaptable and reconfigurable. Instead of a fixed assignment of A/D converters to signal processing paths, the system dynamically selects and assigns functional converters based on test results and actual performance requirements. The lookup table and switching mechanism enable flexible reconfiguration, allowing the chip to adapt to different operational scenarios and maximize the utilization of available functional converters.
2Quantity of substance
If the number of A/D converters on a single chip is increased, then the number of piezoelectric transducing elements that can be supported is increased, but the complexity of ensuring all parameters meet specifications increases
Solution Approach 1:
The patent applies preliminary action by performing comprehensive parameter verification and characterization of each A/D converter during the manufacturing process, before the chip is shipped to the customer. The test results are stored in a lookup table that maps each converter's parameters and performance characteristics. This preliminary verification eliminates the need for complex parameter checking at the customer site, thereby reducing device complexity while supporting a large number of piezoelectric transducing elements.
Solution Approach 2:
The patent implements self-service by enabling the chip to automatically manage its own configuration and converter assignment. The system includes automated testing, characterization, and configuration capabilities that operate without external intervention. The lookup table and control logic automatically select and assign functional converters to appropriate signal processing paths, eliminating the need for manual configuration and reducing the complexity of parameter verification.
3Reliability
If redundant A/D converter circuits are incorporated, then the manufacturing yield is increased by allowing chips with some bad converters to be used, but the device complexity and area increase
Solution Approach 1:
The patent applies preliminary action by testing and identifying functional converters among the redundant set before final chip configuration. The system performs characterization on all A/D converters including redundant ones, stores the results in a lookup table, and pre-determines which converters are functional. This allows the chip to be configured to use only functional converters while ignoring defective ones, thereby improving manufacturing yield without requiring complex runtime decision-making.
Solution Approach 2:
The patent implements universality by designing the redundant A/D converters with the same functional capabilities as the primary converters. All converters in the array, including redundant ones, are designed to be interchangeable and capable of performing the same signal processing functions. This uniform design simplifies the overall system architecture and control logic, as the same selection and assignment mechanisms can be applied to any functional converter regardless of its position or original intended purpose.
Data Source
AI summary
The manufacturing yield of an A/D converter semiconductor chip is significantly increased by utilizing a number of A/D converter circuits that include a group of redundant A/D converter circuits. As a result, the semiconductor chip can be wired to form a “good” A/D converter semiconductor chip as long as the number of “bad” A/D converter circuits does not exceed the number of redundant A/D converter circuits.