Redundant Analog Inference IC for Image Sensor Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current systems face inefficiencies in processing image data from image sensors, particularly in performing intensive computations like those required for image segmentation and object recognition, due to the need for data transmission to general-purpose microprocessors, which can be resource-intensive and inefficient.
Innovation Solution
An integrated circuit device is configured with an image sensing pixel array, a memory cell array, and circuits that perform inference computations using hybrid bonding to directly connect the image sensor chip and memory chip to a logic wafer, enabling efficient multiplication and accumulation operations within the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If image data is transmitted from image sensors to general-purpose microprocessors for processing, then computation flexibility is improved, but transmission efficiency and processing speed deteriorate
Solution Approach 1:
The system segments computation tasks into two parts: intensive multiplication and accumulation operations are performed locally at the image sensor using specialized circuits, while less intensive processing is handled by general-purpose microprocessors. This segmentation allows each component to operate in its optimal performance zone, resolving the contradiction between flexibility and speed.
Solution Approach 2:
A specialized computation circuit acts as an intermediary between the image sensor and general-purpose microprocessor. This intermediary handles intensive computations locally, reducing the burden on both the sensor and microprocessor while maintaining system flexibility. The intermediary enables parallel processing paths that improve overall productivity.
2Productivity
If specialized circuits are used for multiplication and accumulation operations, then computation performance is improved, but device complexity increases
Solution Approach 1:
The specialized computation circuits are designed with multi-functionality, capable of performing various types of intensive computations (multiplication, accumulation, and other neural network operations) using a unified architecture. This universality reduces the need for multiple dedicated circuits for different operations, thereby controlling device complexity while maintaining high computation performance.
3Loss of energy
If data is processed locally at the image sensor, then transmission requirements are reduced, but processing capability must be increased
Solution Approach 1:
The image sensor incorporates localized computation capabilities specifically optimized for intensive multiplication and accumulation operations. Rather than making the entire sensor complex, only specific regions or modules are enhanced with specialized circuits, achieving the necessary processing capability while controlling overall device complexity and reducing transmission energy requirements.
Data Source
AI summary
A device configured with redundant computations to improve reliability of using memory cells to perform operations of multiplication and accumulation. The device can have a memory cell array and a logic circuit. Each respective memory cell in the memory cell array has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation and programmable in a second mode, different from the first mode, to store data. The memory cell array has a plurality of regions operable in parallel to perform redundant operations of multiplication and accumulation. The logic circuit is configured to compare a plurality of results, generated from the redundant operations of multiplication and accumulation performed using the plurality of regions respectively, to select an output result from the plurality of results.