Redundant Bit Encoding for Error Control Without Longer Codewords
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing error control codes for digital information transfer and storage face a trade-off between high error correction/detection capability and efficiency, as longer redundant bits reduce data transfer efficiency.
Innovation Solution
An information processing device that generates a redundant bit sequence functioning as both error control and parity bits for divided information bit sequences, minimizing the increase in bit length while improving error correction/detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error control codes with high error correction/detection capability are used, then error correction/detection accuracy is improved, but the bit length of redundant bits increases and transfer efficiency declines
Solution Approach 1:
The patent makes the redundant bits serve multiple functions: they act as both error control code components for overall error correction/detection and as parity bits for divided information bit sequences. This multi-functionality allows the system to achieve high error correction/detection capability while keeping the redundant bit length minimal, thus resolving the contradiction between reliability and transfer efficiency
Solution Approach 2:
The invention merges the error control function and parity check function into a single redundant bit sequence. By combining these two previously separate functions into one unified structure, the patent eliminates the need for separate parity bits, thereby maintaining transfer efficiency while achieving high error correction/detection accuracy
Data Source
AI summary
An information processing device implements error control including at least one of error detection and error correction. The device comprises an information bit sequence acquiring unit and an encoder. The information bit sequence acquiring unit acquires an information bit sequence. The encoder generates a redundant bit sequence enabling execution of error control of the entire information bit sequence, the redundant bit sequence being generated through encoding by a predetermined code based on the information bit sequence and generates a codeword that includes the information bit sequence and the redundant bit sequence. The encoder generates the redundant bit sequence in such a way that one or more bits contained in the redundant bit sequence each functions as a parity bit for one of a plurality of divided information bit sequences produced by dividing the information bit sequence.