Redundant Bond Pad Routing for Contamination-Tolerant Die Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Manufacturing operations in semiconductor devices produce debris that contaminates bonding pads, leading to faulty connections and reduced manufacturing yield, especially when pad pitches are scaled down.
Innovation Solution
Incorporating redundant structures such as routing layers and redundant via paths to interconnect bonding pads, providing alternative electrical paths to compensate for faulty bonds and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manufacturing operations are performed to produce semiconductor devices, then productivity is improved, but debris is generated that contaminates bonding pads and reduces manufacturing yield
Solution Approach 1:
The patent applies preliminary action by forming redundant conductive pads and routing structures before the bonding operation. This allows the device to have pre-configured alternative paths that can be activated if contamination occurs during manufacturing, thereby maintaining productivity while compensating for potential contamination issues.
Solution Approach 2:
The patent implements beforehand cushioning by creating redundant conductive paths and bonding pad structures that serve as backup mechanisms. These redundant structures are prepared in advance to cushion against the harmful effects of debris contamination, ensuring that single-point failures do not compromise the entire bonding operation.
2Area of moving object
If bonding operations are performed with scaled down pad pitches, then device integration density is improved, but debris contamination has a greater impact on bonding reliability
Solution Approach 1:
The patent applies dimensionality change by extending the solution from two-dimensional pad layouts to three-dimensional routing structures with multiple layers. Redundant conductive paths are formed in different spatial dimensions, allowing signals to bypass contaminated pads through alternative vertical and horizontal routes, thereby maintaining reliability despite reduced pad areas.
Solution Approach 2:
The patent implements parameter changes by modifying the electrical path configuration rather than relying solely on physical pad dimensions. By changing the routing topology to include multiple conductive paths with different geometries and layers, the system compensates for the reduced robustness inherent in scaled-down pad pitches.
3Reliability
If redundant conductive pads and routing structures are added, then bonding reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing redundant conductive pads and routing structures that serve multiple functions: they act as normal bonding paths during standard operation and as backup paths when contamination occurs. This multi-functionality reduces the need for separate dedicated backup structures, thereby limiting the increase in device complexity while maintaining improved reliability.
Solution Approach 2:
The patent implements copying by creating simplified duplicate versions of conductive paths rather than entirely new complex structures. The redundant routing layers replicate essential connection topologies in alternative configurations, providing backup capability with minimal additional complexity by reusing proven design patterns.
4Productivity
If redundant via paths are implemented, then manufacturing yield is improved, but fabrication process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the bonding pad structure into multiple independent conductive segments across different routing layers. Each segment can function independently, and redundant vias connect these segments through alternative paths. This segmentation allows the fabrication process to use standard multi-layer routing techniques without requiring entirely new process steps, thereby improving yield while limiting complexity increases.
Data Source
AI summary
Methods, systems, and devices for redundant bond pads in stacked semiconductor architectures are described. A semiconductor device may be formed one or more redundant structures. A memory chip and a logic die may be formed with a redistribution layer that interconnects multiple bonding pads together. The redistribution layer may couple the bonding pads with a common via, where the common via interfaces with circuitry of a respective device. Additionally, or alternatively, a memory chip and a logic die may be formed with redundant via paths that form parallel electrical paths. The redundant via paths may couple device circuitry with respective bonding pads of a device. The memory chip and the logic die may be bonded together to form a semiconductor device.