Redundant Circuit Assignment for Semiconductor Memory Yield
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Solution Overview
Problem
The challenge in semiconductor memory devices is to efficiently utilize redundant circuits to repair fail bits while ensuring all fail bits are addressed, as existing methods often lead to repeated repairs, increased costs, and reduced yield due to inefficient distribution and utilization of redundant resources.
Innovation Solution
A method that involves executing multiple test items to acquire position data of fail bits, determining redundant circuit assignments, and optimizing the distribution of local and global redundant circuits to ensure all fail bits are within the repair range, thereby reducing the number of assigned circuits and avoiding repeated repairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a preset number of redundant circuits are additionally arranged in a storage array area to repair fail bits, then the memory reliability is improved, but the device complexity increases
Solution Approach 1:
The patent divides the storage array into multiple subdomains and segments, allowing redundant circuits to be assigned locally within each segment rather than globally across the entire array. This segmentation enables independent repair operations in each segment, improving reliability for local failures while reducing the complexity of global redundant circuit management.
Solution Approach 2:
The patent implements local redundant circuit assignment where each segment has its own dedicated redundant circuits assigned based on local fail bit positions. This local quality approach ensures that redundant resources are optimally positioned to repair local failures, improving memory reliability while avoiding the complexity of coordinating global redundant circuit assignment across the entire array.
2Manufacturing precision
If multiple test items are executed to acquire complete fail bit position data, then the manufacturing precision of repair assignment is improved, but the productivity decreases
Solution Approach 1:
The patent executes test items in multiple stages, performing preliminary testing and initial fail bit detection before final redundant circuit assignment. This preliminary action allows the system to identify and assign redundant circuits for clearly identified failures early in the process, improving repair assignment precision while reducing the need for extensive re-testing and re-assignment operations.
Solution Approach 2:
The patent implements a dynamic testing and assignment process where the scope and depth of testing adapt based on initial results. If fail bits are identified in the first test stage, redundant circuits are assigned immediately for those failures. Subsequent tests focus only on remaining unassigned areas, dynamically adjusting the testing scope to maintain high precision while improving productivity.
3Device complexity
If the number of assignable local redundant circuits is limited, then the device complexity is reduced, but the reliability decreases when fail bits exceed the repair range
Solution Approach 1:
The patent divides the storage array into multiple segments with dedicated local redundant circuits for each segment. When fail bits exceed the repair range of local redundant circuits in one segment, the system can independently manage each segment's redundant resources, maintaining reliability for local failures while keeping device complexity manageable through localized rather than global redundant circuit management.
Solution Approach 2:
The patent introduces a redundant circuit assignment mechanism that acts as an intermediary between local and global repair needs. When local redundant circuits are insufficient, the system can coordinate with adjacent segments or global redundant resources through this assignment mechanism, ensuring reliability is maintained while avoiding the complexity of direct global management.
4Productivity
If redundant circuits are assigned based on first test data only, then the productivity is improved, but the manufacturing precision of repair assignment deteriorates when additional fail bits are discovered
Solution Approach 1:
The patent performs preliminary redundant circuit assignment based on first test data to quickly repair identified failures and improve productivity. Subsequent test items then focus on detecting additional fail bits, and the system performs supplementary assignment for these newly discovered failures, ensuring high repair assignment precision without sacrificing the productivity gains from early assignment.
Solution Approach 2:
The patent implements a dynamic redundant circuit assignment process that adapts as testing progresses. Initial assignments are made based on first test data to quickly address known failures, improving productivity. As subsequent tests reveal additional fail bits, the system dynamically updates assignments to ensure complete coverage, maintaining manufacturing precision while preserving the productivity benefits of early assignment.
Data Source
AI summary
A redundant circuit assigning method a includes: first test item is executed and first test data is acquired; a first redundant circuit assigning result including the number of assigned local redundant circuits and position data of the assigned local redundant circuits is determined according to the first test data; a second test item is executed and second test data is acquired; when fail bits acquired during execution of the second test item include one or more fail bits beyond the repair range of the assigned local redundant circuits and assigned global redundant circuits, and the assignable redundant circuits have been assigned out, target position data of fail bits in a target subdomain and a related subdomain is acquired based on the first test data and the second test data; and a second redundant circuit assigning result is determined according to the first test data and the second test data.