Redundant Clock Distribution via Distributed Flip-Flop
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Solution Overview
Problem
Existing redundant synchronous clock distribution systems face delays in switchover processes due to software-controlled consistency of output clock selection, leading to potential system downtime when the master clock fails, as the differential wander between PLLs on each board takes too long to stabilize.
Innovation Solution
A redundant synchronous clock distribution system employing a distributed flip-flop circuit with halves located on each clock module, allowing for a fast and safe switchover between master and slave modes without requiring complex software or hardware, utilizing a flip-flop-circuit with detection circuits to manage interconnection states and prevent oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-controlled master and slave states are used to control output clock selection multiplexers, then clock source switchover can be managed, but switchover time becomes too long exceeding maximum allowed time
Solution Approach 1:
The patent replaces the software-controlled switchover mechanism with a hardware-based distributed flip-flop circuit. This hardware implementation eliminates software processing delays and communication overhead between clock boards, enabling instantaneous or near-instantaneous switchover that meets maximum allowed time requirements while maintaining reliable clock source switching.
Solution Approach 2:
The distributed flip-flop circuit acts as an intermediary mechanism between the master and slave clock modules. It coordinates the switchover process through hardware-level signal exchange, eliminating the need for lengthy software communication protocols while ensuring consistent state management across both clock boards during transitions.
2Reliability
If external reference switches over and PLLs lock onto new clock reference, then clock synchronization is updated, but differential wander between PLLs takes several hours to stabilize
Solution Approach 1:
The distributed flip-flop circuit prepares and coordinates the switchover action in advance at the hardware level. By pre-synchronizing the master and slave states through hardware signals before the actual clock reference change takes effect, the system minimizes the differential wander buildup and accelerates the stabilization process from hours to a much shorter duration.
3Speed
If distributed flip-flop circuit is used for switchover control, then switchover speed is improved, but circuit complexity increases
Solution Approach 1:
The flip-flop circuit is segmented into distributed components located on separate clock boards rather than centralized. Each clock board contains a portion of the flip-flop logic that operates independently but coordinates with the other board through simple hardware signals. This segmentation reduces the complexity of any single board while achieving fast switchover through parallel hardware operation.
Data Source
AI summary
A redundant synchronous clock distribution system is provided comprising at least a first and a second clock module and first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system. Each of the first and second clock modules are adapted to act as a master clock module or a slave clock module. A clock switchover module is adapted to switch each of the first and second clock modules to change between the master mode and the slave mode. The clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part, wherein the first circuit part is located on the first clock module and the second circuit part is located on the second clock module.