Redundant Clock Synchronization with Asynchronous Leader Switching

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Solution Overview

Problem

Fault-tolerant computing systems require reliable clock synchronization across multiple redundant computers to maintain operation in the event of failures, but existing systems struggle with rapid changes in clock offset values indicating oscillator malfunctions, necessitating a method to detect and adapt to such failures.

Innovation Solution

A computing system with an oscillator, counter, communications interface, and processing component that determines time differentials with other systems, maintains a synchronized clock, and re-synchronizes with an alternate system upon detecting a failure criterion, such as a rapidly changing offset value, ensuring continuous operation by selecting a new leader and updating offset values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the system maintains synchronization with a single leader computing system, then the clock synchronization is simple and stable, but the system reliability decreases when the leader fails

Engineering Contradiction:
Improvesystem reliabilityVSAvoidsynchronization complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system pre-calculates and stores offset values for multiple potential leader computing systems before any failure occurs. When the current leader fails, the system can immediately switch to an alternate leader using the pre-computed offset values, eliminating the need for time-consuming resynchronization calculations during failure recovery.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically switches between different leader computing systems based on their operational status. Instead of statically relying on a single leader, the system maintains the ability to adaptively change leaders, with the processing component monitoring leader health and transitioning to alternate leaders when failures are detected.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If the system rapidly switches to an alternate leader upon failure, then the recovery time is minimized, but the difficulty of detecting and measuring leader failure increases

Engineering Contradiction:
Improverecovery timeVSAvoidfailure detection difficulty
Core Design Contradiction:
Loss of timeVSDifficulty of detecting and measuring

Solution Approach 1:

The processing component continuously monitors the leader computing system for failure criteria and uses this feedback to trigger immediate switching to alternate leaders. The system employs offset value changes as an indicator of potential leader issues, allowing proactive detection and response before complete failure occurs.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system prepares alternate leader offset values in advance, so when a failure is detected, the switch can occur immediately without calculation delays. This pre-computation approach minimizes recovery time while maintaining simple failure detection based on pre-established criteria.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the system maintains offset values for multiple computing systems, then the fault tolerance is improved, but the memory requirements and processing complexity increase

Engineering Contradiction:
Improvefault toleranceVSAvoidmemory resources
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system segments the offset value storage by maintaining separate offset values for each potential leader computing system. This organization allows efficient access to specific leader offsets while maintaining a manageable structure that scales with the number of potential leaders, balancing fault tolerance with resource usage.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11353918B2Asynchronous timing exchange for redundant clock synchronization
Publication Date: 2022.06.07 THE CHARLES STARK DRAPER LABORATORY INC
  • US11353918B2 patent drawing
  • US11353918B2 patent drawing
  • US11353918B2 patent drawing

AI summary

The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.