Redundant Clock Switch With Phase Alignment
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Solution Overview
Problem
Computer processing units are vulnerable to errors from external oscillator clock signals, leading to reliability issues and potential system failures, which can result in costly downtime and reboot requirements.
Innovation Solution
A redundant clock switch (RCS) system that derives a reference clock signal from a primary oscillator and aligns a secondary oscillator signal with a phase offset to ensure continuous operation by switching to the secondary signal if an error is detected in the primary signal, minimizing phase jump and maintaining system reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single oscillator is used to generate the clock signal, then the device complexity is reduced, but the reliability deteriorates due to vulnerability to oscillator errors
Solution Approach 1:
The clock system is segmented into multiple independent oscillators (primary and secondary), each capable of generating clock signals independently. This segmentation allows the system to maintain reliability through redundancy while managing complexity by organizing each oscillator with its dedicated phase rotator and multiplexer components.
Solution Approach 2:
The secondary oscillator is prepared in advance as a standby source, with its phase pre-aligned to the primary clock signal through the phase rotator. This preliminary preparation ensures that when a failover is needed, the transition is seamless and immediate, maintaining system reliability without requiring complex real-time adjustment mechanisms.
2Reliability
If a redundant oscillator is added to the system, then the reliability is improved, but the device complexity increases due to additional components
Solution Approach 1:
The phase rotator circuit serves multiple functions: it aligns the phase of the secondary oscillator to the primary clock signal during normal operation, and simultaneously prepares the secondary signal for immediate failover. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby managing complexity while maintaining reliability.
Solution Approach 2:
The multiplexer acts as an intermediary component that selectively switches between the primary and secondary clock signals based on fault detection. This intermediary manages the complexity of switching by providing a centralized control point, while the fault detection logic monitors both oscillators and triggers appropriate switching to maintain reliability.
3Adaptability or versatility
If the secondary oscillator signal has a frequency or phase offset, then the adaptability to different oscillator sources is improved, but the manufacturing precision deteriorates due to phase alignment requirements
Solution Approach 1:
The phase rotator is designed to dynamically adjust the phase of the secondary oscillator signal to match the primary clock signal. This dynamic adjustment capability allows the system to accommodate oscillators with initial phase or frequency offsets while achieving precise phase alignment through active control, thereby maintaining both adaptability and manufacturing precision.
Solution Approach 2:
The system employs feedback mechanisms where the phase rotator continuously monitors the phase difference between the secondary oscillator and primary clock signal, and adjusts the secondary signal accordingly. This feedback loop ensures precise phase alignment despite variations in oscillator characteristics, maintaining manufacturing precision while preserving adaptability to different oscillator sources.
Data Source
AI summary
A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.