Redundant Network Clock Synchronization via Weighted Averaging
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Solution Overview
Problem
Existing time synchronization methods in critical systems lack sufficient fault tolerance and reliability, particularly in scenarios where single communication links can introduce failures, and existing protocols like IEEE 1588 may be affected by inaccurate time stamps due to clock drift and propagation delays.
Innovation Solution
An electronic apparatus with dual network interfaces synchronizes with a master clock using synchronization messages over multiple networks, combining redundant Ethernet paths with IEEE 1588 protocols to determine accurate clock offsets through weighted averaging of correction parameters based on propagation delays, thereby enhancing synchronization accuracy and fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single communication link is used for time synchronization, then the system structure is simple, but the fault tolerance and reliability are insufficient
Solution Approach 1:
The patent combines multiple communication links (first and second communication links) into a unified time synchronization system. The slave device receives synchronization messages through both links simultaneously and processes them together to determine clock offset, thereby achieving fault tolerance without requiring completely separate synchronization systems.
Solution Approach 2:
The patent segments the time synchronization process into distinct phases: receiving synchronization messages through multiple links, determining propagation delays for each link separately, calculating clock offset based on these delays, and adjusting the clock. This segmentation allows the system to handle multiple links systematically while maintaining manageable complexity.
2Reliability
If synchronization messages are transmitted over multiple networks, then the fault tolerance is improved, but the synchronization accuracy may deteriorate due to different propagation delays
Solution Approach 1:
The patent changes the parameter handling approach by explicitly measuring and compensating for propagation delays in each communication link. Instead of treating all synchronization messages uniformly, the system adjusts timing parameters based on the specific propagation characteristics of each link, thereby maintaining accuracy despite using multiple networks.
Solution Approach 2:
The patent implements a feedback mechanism where the slave device measures propagation delays from synchronization messages received through multiple links and uses this information to adjust its clock offset calculation. This feedback loop ensures that synchronization accuracy is maintained by compensating for variations in propagation delays across different networks.
3Ease of operation
If the first arriving synchronization message is used and other messages are discarded, then the processing is simple, but the reliability is reduced
Solution Approach 1:
The patent merges the processing of multiple synchronization messages received through different communication links into a unified clock offset determination process. Instead of selecting only the first message, the slave device combines information from messages received through both the first and second communication links, thereby improving reliability while maintaining processing efficiency through systematic handling.
4Reliability
If redundant Ethernet solutions are used, then the link failure robustness is increased, but the device complexity increases due to abstraction layers
Solution Approach 1:
The patent applies local quality by handling redundancy specifically at the communication link level rather than requiring system-wide abstraction layers. The slave device independently processes synchronization messages from multiple links using their specific propagation delay characteristics, achieving link failure robustness without imposing complex abstraction layers on the entire time synchronization system.
Data Source
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AI summary
To synchronize a clock (29) of an electronic apparatus (10) with a master clock (63) at least one first synchronization message transmitted over a first network (11) is received at a first network interface (21) and at least one second synchronization message transmitted over a second network (12) is received at a second network interface (22). A first clock correction parameter is determined based on the at least one first synchronization message and a second clock correction parameter is determined based on the at least one second synchronization message. The clock (29) of the electronic apparatus (10) is aligned with the master clock (63) as a function of both the first clock correction parameter and the second clock correction parameter.