Redundant Communication Control Section for EtherCAT Time Synchronization

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Solution Overview

Problem

Conventional EtherCAT master systems with two communication ports face challenges in maintaining time synchronization accuracy, ensuring command consistency, and simplifying software development due to issues with communication path redundancy, leading to decreased performance and increased complexity.

Innovation Solution

An information processor with a redundant communication control section that includes a communication path state determination section and a redundant path switching section, allowing for dynamic switching between communication paths to maintain a logical ring topology, ensuring reliable communication and command consistency without the need for software processing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the EtherCAT master is provided with two communication ports to ensure redundancy, then the reliability of the control system is improved, but the time synchronization accuracy deteriorates due to software processing delays

Engineering Contradiction:
Improvecommunication path redundancyVSAvoidtime synchronization accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent introduces a dedicated redundant communication control section as an intermediary hardware component that manages the two communication ports. This mediator handles packet routing and redundancy management at the hardware level, eliminating software processing delays that would otherwise affect time synchronization accuracy while maintaining communication reliability through redundant paths

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the same packet is transmitted from both communication ports to ensure redundancy, then the reliability is improved, but the device complexity increases due to additional processes needed for command consistency

Engineering Contradiction:
Improvecommunication redundancyVSAvoidsoftware processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The redundant communication control section serves as a hardware intermediary that automatically manages packet transmission through both communication ports. It handles the complexity of coordinating transmissions, managing command consistency, and routing packets through the appropriate path based on communication state, thereby eliminating the need for complex software processing while maintaining reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system enables self-service by allowing the redundant communication control section to automatically detect communication path states and switch between ports without external intervention. The hardware component autonomously manages redundancy coordination, packet routing, and error handling, reducing the burden on software development and system operators

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If software processing is used to manage redundant communication paths, then the adaptability is improved, but the productivity deteriorates due to software processing delays in real-time control

Engineering Contradiction:
Improvecommunication path management flexibilityVSAvoidreal-time control speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces software-based communication path management with a hardware-based redundant communication control section. This substitution moves the management function from the software layer to the hardware layer, eliminating software processing delays while maintaining the flexibility to adapt to different communication states through dedicated circuitry and logic

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9148297B2Information processor and control network system
Publication Date: 2015.09.29 HITACHI IND EQUIP SYST CO LTD
  • US9148297B2 patent drawing
  • US9148297B2 patent drawing
  • US9148297B2 patent drawing

AI summary

An information processor capable of ensuring time synchronization accuracy, ensuring EtherCAT command consistency, and easily developing the software based on a 2-port configuration even when a communication path error occurs includes: an arithmetic section; at least two communication sections each including a transmission section and a reception section; and a redundant communication control section that controls a communication path between the arithmetic section and the communication section. The redundant communication control section includes: a communication path state determination section that determines a network path state; and a redundant path switching section that switches connection between the arithmetic section and at least two communication sections.