Standby Dual Redundant Controller Equalization Bus

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Solution Overview

Problem

In standby dual redundant systems with multiple CPUs performing different calculations, the existing configuration requires a separate bus controller for each CPU, leading to increased circuit scale and simultaneous data transfer limitations between equalization and I/O operations.

Innovation Solution

A standby dual redundant system with independent equalization and I/O bus controllers allows for simultaneous data transmission/reception between controllers and I/O boards, eliminating the need for separate bus controllers for each CPU by using a dedicated equalization data bus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate bus controller is provided for each CPU to enable data equalization, then data equalization capability is improved, but the circuit scale is enlarged

Engineering Contradiction:
Improvedata equalization capabilityVSAvoidcircuit scale
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the bus controller functionality into two distinct types: I/O bus controllers (one per CPU board for I/O operations) and equalization bus controllers (shared for data equalization between active and standby controllers). This segmentation allows each controller type to be optimized for its specific function, reducing the need for redundant controllers while maintaining full data equalization capability across all CPUs.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If the same system bus is used for both equalization data transmission and I/O board data transmission, then device complexity is reduced, but simultaneous transmission capability is lost

Engineering Contradiction:
Improvebus controller configurationVSAvoidsimultaneous transmission capability
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the data transmission pathways into two separate bus systems: the I/O bus for communication between CPUs and I/O boards, and the equalization data bus for synchronizing data between active and standby controllers. This segmentation enables simultaneous operations on both buses without interference, achieving both low complexity and high productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces separate bus controllers as intermediary components: I/O bus controllers manage I/O data transmission while equalization bus controllers manage synchronization data transmission. These intermediaries coordinate the different data flows, enabling simultaneous operations without direct conflict on shared resources.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2849005B1Standby dual redundant system
Publication Date: 2019.08.07 MITSUBISHI ELECTRIC CORP
  • EP2849005B1 patent drawingFigure 1
  • EP2849005B1 patent drawingFigure 2
  • EP2849005B1 patent drawingFigure 3

AI summary

A standby dual redundant system (100) includes two controllers (10a, 10b) having equalization bus controllers (12a, 12b) for transmitting equalization data used for equalizing device states of an active-side controller (1a) and a standby-side controller (10b), from the active-side controller (10a) to the standby-side controller (10b) via an equalization data bus (20), the equalization bus controllers being independent from I/O bus controllers (13a, 13b).