Redundant High-Frequency Counter for Glitch-Free PLL Locking
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Solution Overview
Problem
All-digital PLL frequency synthesizers face issues with synchronous and asynchronous counter topologies, where synchronous counters have high power consumption and long internal loops, while asynchronous counters suffer from glitches due to internal flip-flop delays, and frequency division does not adequately solve these problems.
Innovation Solution
Introducing redundancy in the counter circuit by allowing the second counting section to change its state before the first section completes its cycle, enabling detection and correction of invalid states through a decoder, which ensures accurate phase detection and lock in the PLL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a synchronous +1-counter is used with enough bits to guarantee locking to the correct frequency, then frequency locking accuracy is improved, but power consumption increases and internal loop length increases limiting operation speed
Solution Approach 1:
The counter is divided into multiple counting sections (first counting section, second counting section, etc.) that operate asynchronously. Each section processes a portion of the counting function, allowing the system to achieve accurate frequency locking without requiring a single large synchronous counter that would consume excessive power and have long internal loops.
Solution Approach 2:
The patent employs an asynchronous counter topology where counting sections operate at different times rather than simultaneously. The second counting section is enabled only when the first counting section detects a specific state, creating a dynamic, time-multiplexed operation that reduces overall power consumption while maintaining counting accuracy.
2Productivity
If an asynchronous counter topology is used to reduce power consumption and internal loop length, then power consumption and operation speed are improved, but glitches occur due to internal flip-flop delays causing incorrect phase detection
Solution Approach 1:
The first counting section performs a preliminary counting operation and monitors its own state. Only when it detects a specific predetermined state does it enable the second counting section. This preliminary action ensures that the second section starts counting at the correct moment, preventing glitches and ensuring accurate phase detection before the main counting function begins.
Solution Approach 2:
The first counting section provides feedback control for enabling the second counting section. When the first section detects its specific state, it generates an enable signal for the second section. This feedback mechanism ensures that the asynchronous counting sections are properly synchronized, eliminating glitches while maintaining the speed advantages of asynchronous operation.
3Speed
If frequency division is used to reduce counter input frequency, then operation speed issues are mitigated, but it does not adequately solve the glitch problem from asynchronous counting delays
Solution Approach 1:
Instead of simply dividing the frequency, the patent uses the first counting section to perform a preliminary state-detection function. This section actively monitors and detects when specific conditions are met, then triggers the second counting section. This preliminary action approach is more effective than frequency division because it ensures proper timing and synchronization, preventing glitches while maintaining accurate phase detection.
Data Source
AI summary
A counter circuit and method of controlling such a counter circuit, including a first counting section that counts in accordance with a state-cycle, and a second counting section clocked by the first counting section. At least one invalid counting state is introduced by controlling the second counting section to change its state before the first counting section has completed the state-cycle; and the invalid counting state is then detected and corrected. Thereby, some redundancy is introduced in the counter, which can be used to detect and correct incomplete switching of counter states.