Redundant CPU Assignment for Fail-Safe Parallel Computing
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Solution Overview
Problem
In complex systems requiring high safety and reliability, such as railway signaling systems, ensuring sound data transmission and reception between multiple fail-safe CPUs for parallel calculation processing is challenging, especially with asynchronous operation and potential transmission/reception errors.
Innovation Solution
A fail-safe computer system with a master CPU and multiple processing CPUs, where input data is assigned to both a priority and reserve processing CPU, with verification and switching mechanisms to ensure consistent calculation results and maintain reliability, even in the presence of transmission errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple fail-safe CPUs are used for parallel calculation processing, then processing power is improved, but data transmission and reception soundness becomes more difficult to ensure
Solution Approach 1:
The patent applies copying by transmitting the same input data to multiple processing CPUs (priority processing CPU and reserve processing CPU) to perform duplicate calculations. The calculation results are then compared to verify consistency, ensuring data transmission soundness while maintaining high processing power through parallel computation.
Solution Approach 2:
The patent implements feedback mechanisms where calculation results from multiple CPUs are transmitted back to the master CPU for comparison. This feedback loop enables verification of data transmission integrity and ensures that parallel processing maintains reliability through result consistency checking.
2Reliability
If data is transmitted to both priority and reserve processing CPUs for verification, then reliability is improved, but data transmission volume increases
Solution Approach 1:
The patent extracts only the essential data elements for verification purposes. Instead of transmitting all intermediate calculation data, only the final calculation results are transmitted back to the master CPU for comparison, reducing data transmission volume while maintaining reliability through result verification.
3Reliability
If calculation results are verified between priority and reserve CPUs, then safety is maintained, but processing time increases
Solution Approach 1:
The patent performs preliminary actions by transmitting input data to both priority and reserve processing CPUs simultaneously at the beginning of the calculation process. Both CPUs perform calculations in parallel, and the results are compared afterward, which minimizes verification time while maintaining safety through concurrent processing.
Data Source
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AI summary
In a fail-safe computer system (1), a master CPU (12) determines and assigns, for each assignment program, a priority processing CPU and a reserve processing CPU to be in charge of calculation processing of the assignment program, transmits given input data for the assignment program to the priority processing CPU and the reserve processing CPU to which the assignment program is assigned, causes the priority processing CPU and the reserve processing CPU to execute calculation processing based on the input data subsequent to a previous calculation process, and obtains calculation result data. The priority processing CPU executes the calculation processing based on the input data, and transmits the calculation result data to the master CPU (12) and the reserve processing CPU. The reserve processing CPU executes the calculation processing based on the input data, and transmits the calculation result data to the master CPU (12).