Redundant Cryptographic Processing for Semiconductor Functional Safety
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Solution Overview
Problem
Existing semiconductor devices face challenges in simultaneously meeting security and functional safety requirements while minimizing circuit size, as duplicating AES circuits or entire security configurations leads to increased size and processing overhead.
Innovation Solution
Implementing a redundant control unit with multiple processors, independent encryption processing units, and error detection mechanisms to ensure secure and safe data communication, while using error detection and correction codes to verify processing results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the AES circuit is duplicated to satisfy functional safety requirements, then reliability is improved, but device complexity increases
Solution Approach 1:
The encryption unit is segmented into multiple independent encryption processing units (first encryption processing unit and second encryption processing unit), each capable of independent encryption operations. This segmentation allows functional safety through redundancy while maintaining manageable circuit complexity by dividing the overall encryption function into modular components.
Solution Approach 2:
The patent implements copying by creating duplicate encryption processing units that perform identical encryption functions. The first and second encryption processing units are copies of each other, enabling fail-operational capability where if one unit fails, the other can continue providing security functions, thus satisfying functional safety requirements without requiring complete system duplication.
2Reliability
If the entire security configuration is duplicated to satisfy functional safety requirements, then reliability is improved, but device complexity increases significantly
Solution Approach 1:
The security configuration is segmented into distinct functional modules: control units, encryption units, and data transfer units. Each module can be independently designed and duplicated only where necessary for fail-operational capability, rather than duplicating the entire security system. This modular segmentation reduces overall device complexity while maintaining functional safety.
Solution Approach 2:
The encryption processing units are designed with multi-functionality, capable of performing both security encryption functions and serving as redundant backup units. The same hardware structure serves multiple purposes: primary encryption, standby encryption, and error detection, reducing the need for separate dedicated components and thereby reducing overall circuit size.
3Reliability
If multiple encryption processing units are implemented, then security is improved, but processing overhead increases
Solution Approach 1:
The control unit implements periodic switching between the first and second encryption processing units based on operational status and error detection results. During normal operation, one unit is active while the other serves as standby, with periodic verification of their operational status. This periodic activation and verification reduces processing overhead compared to continuously operating multiple units simultaneously.
Solution Approach 2:
The control unit acts as an intermediary that manages the coordination between multiple encryption processing units and data transfer units. It handles the complexity of switching, error detection, and status verification, allowing the encryption units themselves to focus solely on their core encryption function without additional overhead from management tasks.
4Reliability
If error detection mechanisms are added to data transfer, then reliability is improved, but device complexity increases
Solution Approach 1:
The error detection function is merged with the existing data transfer units rather than being implemented as separate dedicated error detection circuits. The data transfer units incorporate error detection capabilities directly into their transfer logic, allowing simultaneous data transfer and error detection using the same hardware resources, thereby improving reliability without proportionally increasing circuit size.
Solution Approach 2:
The data transfer units are designed with multi-functionality, serving both as data transfer pathways and as error detection mechanisms. The same hardware structures that transfer data between control units and encryption units also perform error detection on the transferred data, eliminating the need for separate error detection circuits and reducing overall device complexity.
Data Source
AI summary
The semiconductor device includes a control unit having redundant processors, a memory storing target data, a secure memory storing a key used for encryption or decryption processing, an cryptographic unit, a secure processor instructing cryptographic processing to the cryptographic unit in response to a request from the control unit, a first bus coupled to the control unit, the memory, the cryptographic unit, and the secure processor, and a second bus coupled to the secure memory, the cryptographic unit, and the secure processor. The control unit communicates with the memory via a predetermined error detection mechanism, the cryptographic unit includes a plurality of cryptographic processors that independently perform cryptographic processing on target data using a key based on an instruction, and each of the plurality of cryptographic processors includes a data transfer unit that performs data transfer with the memory via the error detection mechanism.