Redundant DRAM Data Interfaces for High-Capacity Fault Tolerance
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Solution Overview
Problem
Existing memory systems face limitations in the number of modules that can be connected to a single channel, leading to degraded signaling integrity and reduced signaling rates, while also requiring improvements in reliability to manage hardware faults.
Innovation Solution
The implementation of dual-port DRAM components with redundant and interconnected data interfaces allows for increased module counts per channel, maintaining high signaling speeds and providing flexible routing options to bypass defective data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional modules are added to a memory channel to increase memory capacity, then the memory capacity per channel is improved, but the signaling integrity and signaling rates are degraded
Solution Approach 1:
The memory channel is segmented into multiple independent data paths (first data path, second data path, third data path) that can operate simultaneously. Each path connects to different modules, allowing the channel to serve more modules without overloading a single signaling path, thus maintaining signaling integrity while increasing capacity
Solution Approach 2:
The patent introduces an additional dimension of data path routing by providing multiple independent paths (first, second, and third data paths) between the memory controller and modules. This multi-dimensional routing allows data to traverse different physical paths, reducing interference and maintaining signal quality even as the number of connected modules increases
2Quantity of substance
If additional modules are added to a memory channel to increase memory capacity, then the memory capacity per channel is improved, but the signaling rates are reduced
Solution Approach 1:
The data transfer function is segmented across multiple parallel paths, each capable of operating at full signaling rate. By distributing data traffic across first, second, and third data paths, each path handles a subset of the total data load, allowing all paths to maintain high signaling rates while collectively serving more modules
Solution Approach 2:
Multiple data paths are merged at the memory controller to provide aggregate bandwidth. The controller combines the capacity of first, second, and third data paths, effectively multiplying the available signaling capacity and allowing high-speed operation to be maintained even as the number of connected modules increases
3Reliability
If redundant data interfaces are implemented to provide fault tolerance, then the reliability is improved, but the device complexity is increased
Solution Approach 1:
The redundant data interfaces are designed with multi-functionality, where the same interface structure serves both normal data transfer and fault tolerance functions. The first, second, and third data paths can be dynamically configured for different purposes, reducing the need for entirely separate redundant hardware and thereby limiting the increase in complexity
Solution Approach 2:
The memory controller acts as an intermediary that manages the complexity of multiple data paths. It implements intelligent routing logic that automatically selects appropriate paths based on module status and data flow requirements, shielding the rest of the system from the underlying complexity while maintaining high reliability
4Reliability
If flexible routing options are provided to bypass defective paths, then the reliability is improved, but the device complexity is increased
Solution Approach 1:
The data path configuration is made dynamic, allowing the system to adapt routing in real-time based on detected faults. The memory controller can dynamically activate alternative paths (e.g., switching from first data path to second or third data path) when defects are detected, providing fault tolerance through adaptive reconfiguration rather than static complex routing structures
Data Source
AI summary
A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.