Redundant Enable Protection Circuit for Memory Latch Disturb
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Solution Overview
Problem
Memory devices face issues with latch disturb events, which can lead to erroneous operations or complete failure due to single event upsets, nicked fuses, or other electrical disturbances, causing unintended activation of memory cell repairs.
Innovation Solution
Incorporating an unused redundant enable protection circuit and a no_match circuit to prevent repairs of external memory addresses by forcing a no match signal, thereby overriding any potential duplicate repairs or data overwrites.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant enable circuits are used to repair damaged memory cells, then memory reliability is improved, but the system becomes vulnerable to latch disturb events that can cause erroneous operations
Solution Approach 1:
A protection circuit is introduced as an intermediary between the redundant enable circuit and the memory array. This protection circuit monitors the state of unused redundant enable circuits and prevents them from inadvertently activating, thereby blocking the harmful effect of latch disturb events while allowing legitimate repair operations to proceed
Solution Approach 2:
The protection circuit proactively prevents latch disturb events by detecting potential erroneous activations before they can cause harmful effects. By implementing preliminary protection measures on unused redundant enable circuits, the system counteracts the vulnerability to single event upsets and nicked fuses before they can trigger incorrect repair operations
2Manufacturing precision
If fuse banks are programmed with default addresses for repair, then manufacturing precision is improved, but unused redundant enable circuits may be inadvertently activated during operation
Solution Approach 1:
The protection circuit dynamically monitors and controls the state of redundant enable circuits based on operational conditions. It adaptively enables or disables protection based on whether a match between external addresses and fuse bank addresses is detected, allowing flexible response to different operational scenarios while preventing erroneous activations
Solution Approach 2:
The protection circuit implements feedback mechanisms by continuously monitoring the output of match circuits and adjusting its behavior accordingly. When a match is detected indicating a legitimate repair operation, the protection circuit appropriately responds by allowing the operation to proceed, thereby maintaining reliability while preserving manufacturing precision
3Reliability
If protection circuits are added to prevent latch disturb events, then reliability is improved, but device complexity increases
Solution Approach 1:
The protection function is segmented into modular components including protection circuits, match circuits, and redundant enable circuits that can be independently designed and integrated. This segmentation allows the protection functionality to be added without completely redesigning the entire memory system, thereby limiting the increase in overall device complexity
Solution Approach 2:
The protection circuit is designed to handle multiple types of errors and disturbances through a unified mechanism. By implementing a universal protection approach that addresses latch disturb events, single event upsets, and nicked fuses through a single circuit architecture, the patent avoids the complexity that would result from implementing separate protection circuits for each error type
Data Source
AI summary
A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.