Redundant Error Handler Execution for System Reliability

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Solution Overview

Problem

Conventional information processors face challenges in handling uncorrectable errors in memories, where the error handler may become abnormal, leading to system hangs and inability to identify the error's point of occurrence, especially when errors occur in both memories simultaneously.

Innovation Solution

The information processor employs two processors and two memories, with error handler programs stored on each memory. If one processor fails to complete the error handler, the second processor executes the error handler from the other memory, and both processors sequentially access devices in different orders to extract information, ensuring continued operation and error identification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an error handler program is stored in a single memory and executed by a single processor, then the system structure is simple, but if an uncorrectable error occurs in that memory, the error handler itself may become abnormal causing a system hang and inability to identify the error point

Engineering Contradiction:
Improveerror handling reliabilityVSAvoidsystem structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating redundant error handler programs in different memories (first and second error handler programs in first and second memories respectively). This ensures that if one memory has an uncorrectable error, the other memory's error handler can still execute, providing localized error handling capability that prevents system-wide failure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the error handling function by dividing it into separate error handler programs stored in different memories and executable by different processors. This segmentation ensures that an error in one memory segment does not affect the execution of error handlers in other segments, allowing independent error handling paths.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If the CPU sequentially accesses devices to extract information for error identification, then the information extraction is systematic, but if an error occurs in a device being accessed, the system hangs and remaining devices cannot be accessed

Engineering Contradiction:
Improveerror point identification accuracyVSAvoidsystem operation reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies inversion by having the second processor execute the second error handler program when the first processor fails, and vice versa. This reverse execution path ensures that if one processor-memory pair encounters an error during information extraction, the other processor can continue the extraction process from where it left off, preventing system hangs and ensuring complete error point identification.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent implements preliminary action by pre-storing multiple error handler programs in different memories before errors occur. This preparation ensures that when an uncorrectable error happens during information extraction, a functional error handler is already available to take over and complete the extraction process, avoiding system hangs.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If a single processor executes the error handler program, then the execution flow is simple, but if the processor itself fails or the memory containing the error handler becomes abnormal, the error cannot be handled

Engineering Contradiction:
Improveerror handler execution simplicityVSAvoiderror handling completeness
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent merges the error handling capability across multiple processors and memories by establishing that either the first processor executing the first error handler program or the second processor executing the second error handler program can handle errors. This merging creates a redundant error handling system where the failure of one processor-memory pair does not compromise overall error handling reliability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8020040B2Information processing apparatus for handling errors
Publication Date: 2011.09.13 FUJITSU LTD
  • US8020040B2 patent drawing
  • US8020040B2 patent drawing
  • US8020040B2 patent drawing

AI summary

In the event of occurrence of an error in a memory in an information processor, a first processor that is one of a number of processors executes an error handler program stored in a first memory that is one of a number of memories. If the first processor fails in correctly operating the error handler program, a second processor different from the first processor executes an error handler program stored in a second memory different from the first memory.