Redundant Flip-Flop Test Time Reduction via Shadow Logic
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Solution Overview
Problem
The integration of triple-voting flops in integrated circuits increases test time due to the additional shift cycles required for testing, which is undesirable especially in safety-critical systems where efficiency and reliability are paramount.
Innovation Solution
A digital circuit configuration that operates in both functional and test modes, where redundant flip-flops are used with one flip-flop in a test path and the others as shadow logic, allowing all flip-flops to be tested within a single shift cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple-voting flops are used in integrated circuits, then reliability and fault tolerance are improved, but test time increases due to additional shift cycles required
Solution Approach 1:
The patent segments the testing process by introducing a dedicated test mode that separates the testing function from the functional operation. In test mode, the circuit configuration changes to allow independent testing of each flip-flop within the triple-voting flop, enabling parallel testing of multiple flip-flops simultaneously rather than sequential testing, thus reducing overall test time while maintaining reliability
Solution Approach 2:
The patent implements dynamic reconfiguration of the circuit between functional mode and test mode. The circuit structure is made adaptable by allowing the flip-flops to be dynamically switched between their normal functional operation and a test configuration where they can be independently tested. This dynamic switching enables the same hardware to serve dual purposes without compromising either reliability or test efficiency
2Reliability
If triple-voting flops are used in integrated circuits, then fault detection capability is improved, but test complexity increases due to multiple flip-flops requiring testing
Solution Approach 1:
The patent creates a universal test structure that can test multiple flip-flops within a triple-voting flop using the same testing infrastructure. The test mode enables a single test path to sequentially or parallelly access all three flip-flops, making the test structure multi-functional and eliminating the need for separate testing mechanisms for each flip-flop, thus reducing test structure complexity while maintaining comprehensive fault detection capability
Data Source
AI summary
According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N−1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N−1 number of redundant flip-flops is observed through the functional path to determine faults.