Redundant Floating Gate Memory Cell for Leakage Current
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Solution Overview
Problem
Existing non-volatile memory (NVM) devices face reliability issues due to stress-induced leakage current and other failures, which can result in complete loss of memory storage, and current error correction code methods require additional memory bits and circuitry, leading to inefficiencies and increased complexity.
Innovation Solution
Arranging two or more floating gate devices in a redundant configuration, such as series or parallel configurations, to mitigate the effects of stress-induced leakage current and other failures, maintaining memory storage without complete loss, and reducing area consumption by sharing well regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) methods are used to improve reliability, then data integrity is improved, but additional memory bits and circuit complexity increase
Solution Approach 1:
The patent implements a redundant memory cell structure where a second memory cell is created as a copy of the first memory cell. This redundant cell serves as a backup that can take over if the primary cell fails, providing error correction functionality without requiring complex ECC decoding circuits. The redundancy is achieved through physical duplication rather than computational error correction, thereby reducing circuit complexity while maintaining data integrity.
2Reliability
If additional data bits are used as backup for each single bit of data, then reliability is improved, but area consumption increases significantly
Solution Approach 1:
The patent merges the functionality of multiple memory cells by coupling them in parallel configuration. The first and second memory cells are connected such that they share common bit lines and word lines, allowing them to operate together as a unified redundant unit. This merging approach provides reliability through redundancy while minimizing area consumption by sharing common circuitry and storage structures between the primary and backup cells.
3Reliability
If redundant memory cells are configured in parallel, then reliability is improved by preventing complete data loss, but circuit complexity increases
Solution Approach 1:
The patent employs homogeneous memory cell structures where the first and second memory cells are identical in design and configuration. Both cells use the same floating gate transistor structure, control gate, and connection topology. This homogeneity simplifies the redundant configuration because the same circuit patterns can be replicated, and the same read/write operations apply to both cells, reducing the complexity of managing redundancy while maintaining failure resistance.
Data Source
AI summary
Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, a complex logic circuit function, and/or as part of an RFID tag system.