Redundant High-Precision Anchor for Reproducible Floating-Point Addition
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Solution Overview
Problem
Floating-point arithmetic is non-associative, leading to reproducibility issues and inefficiencies in parallel processing due to rounding and normalization during calculations, making it difficult to achieve consistent results when adding floating-point values in different orders.
Innovation Solution
The use of a redundant high-precision anchor (RHPA) representation, where data values are split into N-bit portions with overlap bits, allowing for parallel addition without carry propagation between lanes, enabling associative operations and efficient accumulation of floating-point numbers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating-point arithmetic is performed using traditional rounding and normalization, then calculation results are obtained, but the operations become non-associative and non-reproducible when performed in different orders
Solution Approach 1:
The patent segments floating-point numbers into multiple N-bit portions with overlap bits, creating a redundant representation where each portion can be processed independently. This segmentation allows parallel addition operations without carry propagation between portions, enabling reproducible results while improving parallel processing capability.
Solution Approach 2:
The patent changes the representation parameter from standard floating-point format to a redundant format with overlap bits. By modifying how numbers are represented (using M bits to represent P-bit values where M > P), the system achieves both reproducibility and parallel processing efficiency.
2Reliability
If sequential addition is used to ensure reproducible floating-point results, then calculation accuracy is maintained, but processing speed decreases
Solution Approach 1:
By dividing the floating-point representation into multiple N-bit portions with overlap bits, the patent enables parallel addition operations. Each portion can be added simultaneously without affecting others, achieving both reproducibility (through consistent overlap bit handling) and speed (through parallel processing).
Solution Approach 2:
The overlap bits act as intermediaries that carry significance information between portions. By including overlap bits in each N-bit portion, the system maintains reproducibility while allowing parallel processing, as the overlap bits provide the necessary carry information without requiring sequential processing.
3Productivity
If redundant representation with overlap bits is used, then parallel processing is enabled, but data structure complexity increases
Solution Approach 1:
The patent uses parameter changes by defining M > P > N, where M is the total bits, P is the significant bits, and N is the portion size. This parameter relationship systematically controls the redundancy level, enabling parallel processing while managing complexity through a clear mathematical framework.
Solution Approach 2:
The patent applies homogeneity by using uniform N-bit portions throughout the representation, with each portion having the same structure including overlap bits. This homogeneous structure simplifies the processing logic despite the increased data width, as the same operations can be applied to each portion consistently.
Data Source
AI summary
Processing circuitry is provided to perform an overlap propagating operation on a first data value to generate a second data value, the first and second data values having a redundant representation representing a P-bit numeric value using an M-bit data value comprising a plurality of N-bit portions, where M>P>N. In the redundant representation, each N-bit portion other than a most significant N-bit portion includes a plurality of overlap bits having a same significance as a plurality of least significant bits of a following N-bit portion. Each N-bit portion of the second data value other than a least significant N-bit portion is generated by adding non-overlap bits of a corresponding N-bit portion of the first data value to the overlap bits of a preceding N-bit portion of the first data value. This provides a faster technique for reducing the chance of overflow during addition of the redundantly represented M-bit value.